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    DUAL SILICIDE VIA CONTACT STRUCTURE AND PROCESS
    1.
    发明申请
    DUAL SILICIDE VIA CONTACT STRUCTURE AND PROCESS 有权
    双硅胶通过接触结构和工艺

    公开(公告)号：US20060051959A1

    公开(公告)日：2006-03-09

    申请号：US10711298

    申请日：2004-09-09

    申请人： Michael Iwatake ,  Kevin Mello ,  Matthew Oonk ,  Amanda Piper ,  Yun Wang ,  Keith Wong

    发明人： Michael Iwatake ,  Kevin Mello ,  Matthew Oonk ,  Amanda Piper ,  Yun Wang ,  Keith Wong

    IPC分类号： H01L21/4763

    CPC分类号： H01L21/28518 ,  H01L21/76877

    摘要： A via contact is provided to a diffusion region at a top surface of a substrate which includes a single-crystal semiconductor region. The via contact includes a first layer which consists essentially of a silicide of a first metal in contact with the diffusion region at the top surface. A dielectric region overlies the first layer, the dielectric region having an outer surface and an opening extending from the outer surface to the top surface of the substrate. A second layer lines the opening and contacts the top surface of the substrate in the opening, the second layer including a second metal which lines a sidewall of the opening and a silicide of the second metal which is self-aligned to the top surface of the substrate in the opening. A diffusion barrier layer overlies the second layer within the opening. A third layer including a third metal overlies the diffusion barrier layer and fills the opening.

    摘要翻译： 通孔接触被提供到包括单晶半导体区域的衬底的顶表面处的扩散区域。 通孔接触包括第一层，其基本上由与顶表面上的扩散区接触的第一金属的硅化物组成。 电介质区域覆盖在第一层上，电介质区域具有外表面和从衬底的外表面延伸到顶表面的开口。 第二层将开口划线并与开口中的基板的顶表面接触，第二层包括将开口的侧壁排列的第二金属和与第二金属的顶表面自对准的第二金属的硅化物 基材在开口处。 扩散阻挡层覆盖开口内的第二层。 包括第三金属的第三层覆盖扩散阻挡层并填充开口。

    Fabrication of via contacts having dual silicide layers
    2.
    发明申请
    Fabrication of via contacts having dual silicide layers 审中-公开
    具有双重硅化物层的通孔触点的制造

    公开(公告)号：US20070077753A1

    公开(公告)日：2007-04-05

    申请号：US11633299

    申请日：2006-12-04

    申请人： Michael Iwatake ,  Kevin Mello ,  Matthew Oonk ,  Amanda Piper ,  Yun Wang ,  Keith Wong

    发明人： Michael Iwatake ,  Kevin Mello ,  Matthew Oonk ,  Amanda Piper ,  Yun Wang ,  Keith Wong

    IPC分类号： H01L21/4763

    CPC分类号： H01L21/28518 ,  H01L21/76877

    摘要： A method is provided for fabricating a via contact structure contacting a single-crystal semiconductor diffusion region at a top surface of a substrate. In such method, a first layer is formed in contact with the diffusion region at the top surface, the first layer consisting essentially of a silicide of a first metal. A dielectric region is formed to overlie the first layer. An opening is etched in the dielectric region extending through the first layer to the diffusion region. A second layer is formed to line the opening, the second layer including a second metal. Thereafter, a conductor is deposited within the opening over the second layer, and the substrate is heated to cause the second metal to form a silicide at the top surface.

    摘要翻译： 提供了一种用于制造在衬底的顶表面处接触单晶半导体扩散区的通孔接触结构的方法。 在这种方法中，第一层形成为与顶表面处的扩散区接触，第一层基本上由第一金属的硅化物组成。 形成介电区以覆盖第一层。 在延伸穿过第一层的电介质区域中蚀刻开口到扩散区域。 形成第二层以对开口进行排列，第二层包括第二金属。 此后，在第二层的开口内沉积导体，并且加热衬底以使第二金属在顶表面形成硅化物。

    SILICIDE CAP STRUCTURE AND PROCESS FOR REDUCED STRESS AND IMPROVED GATE SHEET RESISTANCE
    4.
    发明申请
    SILICIDE CAP STRUCTURE AND PROCESS FOR REDUCED STRESS AND IMPROVED GATE SHEET RESISTANCE 审中-公开
    减少应力和改进的栅格电阻的硅胶结构和工艺

    公开(公告)号：US20060163671A1

    公开(公告)日：2006-07-27

    申请号：US10905949

    申请日：2005-01-27

    申请人： Levent Gulari ,  Kevin Mello ,  Robert Purtell ,  Yun-Yu Wang ,  Keith Wong

    发明人： Levent Gulari ,  Kevin Mello ,  Robert Purtell ,  Yun-Yu Wang ,  Keith Wong

    IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

    CPC分类号： H01L21/28052 ,  H01L21/28114 ,  H01L21/28518 ,  H01L29/665

    摘要： A suicide cap structure and method of fabricating a suicide cap having a low sheet resistance. The method provides a semiconductor substrate and a MOSFET structure comprising a gate insulator on the substrate, an Si-containing gate electrode on the gate insulator layer, and source/drain diffusions. Atop the gate electrode and source/drain diffusions is formed a layer of metal used in forming a silicide region atop the transistor gate electrode and diffusions; an intermediate metal barrier layer formed atop the silicide forming metal layer; and, an oxygen barrier layer formed atop the intermediate metal barrier layer. As a result of annealing the MOSFET structure, resulting formed silicide regions exhibit a lower sheet resistance. As the intermediate metal barrier layer comprises a material exhibiting tensile stress, the oxygen barrier layer may comprise a compressive material for minimizing a total mechanical stress of the cap structure and underlying layers during the applied anneal.

    摘要翻译： 一种自杀帽结构和制造具有低薄层阻力的自杀帽的方法。 该方法提供半导体衬底和MOSFET结构，其包括在衬底上的栅极绝缘体，栅极绝缘体层上的含Si栅极电极和源极/漏极扩散。 在栅电极和源极/漏极扩散之上形成用于在晶体管栅极顶部形成硅化物区域和扩散的金属层; 形成在所述硅化物形成金属层顶上的中间金属阻挡层; 以及形成在中间金属阻挡层顶上的氧阻隔层。 作为对MOSFET结构进行退火的结果，所形成的形成的硅化物区域具有较低的薄层电阻。 当中间金属阻挡层包括显示拉伸应力的材料时，氧阻挡层可以包括用于在施加的退火期间最小化盖结构和下层的总机械应力的压缩材料。

    SILICIDE CAP STRUCTURE AND PROCESS FOR REDUCED STRESS AND IMPROVED GATE SHEET RESISTANCE
    5.
    发明申请
    SILICIDE CAP STRUCTURE AND PROCESS FOR REDUCED STRESS AND IMPROVED GATE SHEET RESISTANCE 审中-公开
    减少应力和改进的栅格电阻的硅胶结构和工艺

    公开(公告)号：US20080020535A1

    公开(公告)日：2008-01-24

    申请号：US11866751

    申请日：2007-10-03

    申请人： Levent Gulari ,  Kevin Mello ,  Robert Purtell ,  Yun-Yu Wang ,  Keith Wong

    发明人： Levent Gulari ,  Kevin Mello ,  Robert Purtell ,  Yun-Yu Wang ,  Keith Wong

    IPC分类号： H01L21/336 ,  H01L21/44

    CPC分类号： H01L21/28052 ,  H01L21/28114 ,  H01L21/28518 ,  H01L29/665

    摘要： A silicide cap structure and method of fabricating a silicide cap having a low sheet resistance. The method provides a semiconductor substrate and a MOSFET structure comprising a gate insulator on the substrate, an Si-containing gate electrode on the gate insulator layer, and source/drain diffusions. Atop the gate electrode and source/drain diffusions is formed a layer of metal used in forming a silicide region atop the transistor gate electrode and diffusions; an intermediate metal barrier layer formed atop the silicide forming metal layer; and, an oxygen barrier layer formed atop the intermediate metal barrier layer. As a result of annealing the MOSFET structure, resulting formed silicide regions exhibit a lower sheet resistance. As the intermediate metal barrier layer comprises a material exhibiting tensile stress, the oxygen barrier layer may comprise a compressive material for minimizing a total mechanical stress of the cap structure and underlying layers during the applied anneal.

    摘要翻译： 一种硅化物盖结构和制造具有低薄层电阻的硅化物盖的方法。 该方法提供半导体衬底和MOSFET结构，其包括在衬底上的栅极绝缘体，栅极绝缘体层上的含Si栅极电极和源极/漏极扩散。 在栅电极和源极/漏极扩散之上形成用于在晶体管栅极顶部形成硅化物区域和扩散的金属层; 形成在所述硅化物形成金属层顶上的中间金属阻挡层; 以及形成在中间金属阻挡层顶上的氧阻隔层。 作为对MOSFET结构进行退火的结果，所形成的形成的硅化物区域具有较低的薄层电阻。 当中间金属阻挡层包括显示拉伸应力的材料时，氧阻挡层可以包括用于在施加的退火期间最小化盖结构和下层的总机械应力的压缩材料。