公开(公告)号：US08975613B1

公开(公告)日：2015-03-10

申请号：US12610236

申请日：2009-10-30

申请人： Ronald John Kuse ,  Tony Chiang ,  Michael Miller ,  Prashant Phatak ,  Jinhong Tong

发明人： Ronald John Kuse ,  Tony Chiang ,  Michael Miller ,  Prashant Phatak ,  Jinhong Tong

IPC分类号： H01L21/16 ,  G11C11/00

CPC分类号： H01L45/146 ,  G11C13/0007 ,  G11C13/003 ,  G11C2213/32 ,  G11C2213/51 ,  G11C2213/52 ,  G11C2213/56 ,  G11C2213/71 ,  G11C2213/72 ,  G11C2213/74 ,  G11C2213/76 ,  G11C2213/79 ,  H01L27/2409 ,  H01L27/2463 ,  H01L29/861 ,  H01L45/10 ,  H01L45/12 ,  H01L45/1233 ,  H01L45/1616 ,  H01L45/1641

摘要： Resistive-switching memory elements having improved switching characteristics are described, including a memory element having a first electrode and a second electrode, a switching layer between the first electrode and the second electrode, the switching layer comprising a first metal oxide having a first bandgap greater than 4 electron volts (eV), the switching layer having a first thickness, and a coupling layer between the switching layer and the second electrode, the coupling layer comprising a second metal oxide having a second bandgap greater the first bandgap, the coupling layer having a second thickness that is less than 25 percent of the first thickness.

公开(公告)号：US08465996B2

公开(公告)日：2013-06-18

申请号：US13593116

申请日：2012-08-23

申请人： Michael Miller ,  Prashant Phatak ,  Tony Chiang ,  Xiyang Chen ,  April Schricker ,  Tanmay Kumar

发明人： Michael Miller ,  Prashant Phatak ,  Tony Chiang ,  Xiyang Chen ,  April Schricker ,  Tanmay Kumar

IPC分类号： H01L21/00

CPC分类号： H01L45/16 ,  H01L21/265 ,  H01L21/31155 ,  H01L27/2463 ,  H01L29/8615 ,  H01L45/08 ,  H01L45/10 ,  H01L45/12 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/1608 ,  H01L45/1616 ,  H01L45/1625 ,  H01L45/1641 ,  H01L45/165

摘要： This disclosure provides a method of fabricating a semiconductor device layer and associated memory cell structures. By performing a surface treatment process (such as ion bombardment) of a semiconductor device layer to create defects having a deliberate depth profile, one may create multistable memory cells having more consistent electrical parameters. For example, in a resistive-switching memory cell, one may obtain a tighter distribution of set and reset voltages and lower forming voltage, leading to improved device yield and reliability. In at least one embodiment, the depth profile is selected to modulate the type of defects and their influence on electrical properties of a bombarded metal oxide layer and to enhance uniform defect distribution.

公开(公告)号：US20120205610A1

公开(公告)日：2012-08-16

申请号：US13454392

申请日：2012-04-24

申请人： Prashant Phatak ,  Tony Chiang ,  Michael Miller ,  Wen Wu

发明人： Prashant Phatak ,  Tony Chiang ,  Michael Miller ,  Wen Wu

IPC分类号： H01L45/00

CPC分类号： H01L45/1616 ,  H01L27/2409 ,  H01L27/2463 ,  H01L45/08 ,  H01L45/10 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/146

摘要： A resistive switching memory element including a doped silicon electrode is described, including a first electrode comprising doped silicon having a first work function, a second electrode having a second work function that is different from the first work function by between 0.1 and 1.0 electron volts (eV), a metal oxide layer between the first electrode and the second electrode, the metal oxide layer switches using bulk-mediated switching and has a bandgap of greater than 4 eV, and the memory element switches from a low resistance state to a high resistance state and vice versa.

摘要翻译： 描述了包括掺杂硅电极的电阻式开关存储元件，其包括包括具有第一功函数的掺杂硅的第一电极，具有与第一功函数不同的第二功函数的第二电极在0.1和1.0电子伏特之间 eV），第一电极和第二电极之间的金属氧化物层，金属氧化物层使用体积介导的开关进行开关，并且具有大于4eV的带隙，并且存储元件从低电阻状态切换到高电阻 状态，反之亦然。

公开(公告)号：US20120088328A1

公开(公告)日：2012-04-12

申请号：US13329253

申请日：2011-12-17

申请人： Prashant Phatak ,  Tony Chiang ,  Pragati Kumar ,  Michael Miller

发明人： Prashant Phatak ,  Tony Chiang ,  Pragati Kumar ,  Michael Miller

IPC分类号： H01L21/8239

CPC分类号： H01L45/146 ,  G11C13/0007 ,  G11C2213/32 ,  G11C2213/55 ,  G11C2213/72 ,  H01L27/2409 ,  H01L27/2463 ,  H01L29/8615 ,  H01L45/08 ,  H01L45/10 ,  H01L45/122 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/1616 ,  H01L45/1625 ,  H01L45/1641 ,  H01L45/165 ,  H01L45/1658 ,  H01L47/00

摘要： Non-volatile resistive-switching memories are described, including a memory element having a first electrode, a second electrode, a metal oxide between the first electrode and the second electrode. The metal oxide switches using bulk-mediated switching, has a bandgap greater than 4 electron volts (eV), has a set voltage for a set operation of at least one volt per one hundred angstroms of a thickness of the metal oxide, and has a leakage current density less than 40 amps per square centimeter (A/cm2) measured at 0.5 volts (V) per twenty angstroms of the thickness of the metal oxide.

摘要翻译： 描述了非易失性电阻式切换存储器，包括在第一电极和第二电极之间具有第一电极，第二电极，金属氧化物的存储元件。 使用大容量介导的开关的金属氧化物开关具有大于4电子伏特（eV）的带隙，具有用于金属氧化物的厚度每100埃至少一伏特的设定操作的设定电压，并且具有 漏电流密度小于每平方厘米40安培（A / cm2），每0.5伏（V），金属氧化物厚度每20埃测得。

公开(公告)号：US08049305B1

公开(公告)日：2011-11-01

申请号：US12580196

申请日：2009-10-15

申请人： Michael Miller ,  Prashant Phatak ,  Tony Chiang

发明人： Michael Miller ,  Prashant Phatak ,  Tony Chiang

IPC分类号： H01L29/10

CPC分类号： H01L45/1233 ,  H01L23/5228 ,  H01L23/525 ,  H01L27/2409 ,  H01L45/08 ,  H01L45/146 ,  H01L45/1641 ,  H01L2924/0002 ,  H01L2924/00

摘要： A resistance-change memory device using stress engineering is described, including a first layer including a first conductive electrode, a second layer above the first layer including a resistive-switching element, a third layer above the second layer including a second conductive electrode, where a first stress is created in the switching element at a first interface between the first layer and the second layer upon heating the memory element, and where a second stress is created in the switching element at a second interface between the second layer and the third layer upon the heating. A stress gradient equal to a difference between the first stress and the second stress has an absolute value greater than 50 MPa, and a reset voltage of the memory element has a polarity relative to a common electrical potential that has a sign opposite the stress gradient when applied to the first conductive electrode.

摘要翻译： 描述了使用应力工程的电阻变化存储器件，包括第一层，包括第一导电电极，第一层上方的第二层，包括电阻式开关元件，第二层上方的第三层包括第二导电电极， 在加热存储元件时在第一层和第二层之间的第一界面处在开关元件中产生第一应力，并且其中在第二层和第三层之间的第二界面处在开关元件中产生第二应力 加热。 等于第一应力和第二应力之间的差的应力梯度具有大于50MPa的绝对值，并且存储元件的复位电压具有相对于具有与应力梯度相反的符号的公共电位的极性， 应用于第一导电电极。

公开(公告)号：US20100258781A1

公开(公告)日：2010-10-14

申请号：US12608934

申请日：2009-10-29

申请人： Prashant Phatak ,  Tony Chiang ,  Michael Miller ,  Wen Wu

发明人： Prashant Phatak ,  Tony Chiang ,  Michael Miller ,  Wen Wu

IPC分类号： H01L47/00

CPC分类号： H01L45/1616 ,  H01L27/2409 ,  H01L27/2463 ,  H01L45/08 ,  H01L45/10 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/146

摘要： A resistive switching memory element including a doped silicon electrode is described, including a first electrode comprising doped silicon having a first work function, a second electrode having a second work function that is different from the first work function by between 0.1 and 1.0 electron volts (eV), a metal oxide layer between the first electrode and the second electrode, the metal oxide layer switches using bulk-mediated switching and has a bandgap of greater than 4 eV, and the memory element switches from a low resistance state to a high resistance state and vice versa.

摘要翻译： 描述了包括掺杂硅电极的电阻式开关存储元件，其包括包括具有第一功函数的掺杂硅的第一电极，具有与第一功函数不同的第二功函数的第二电极在0.1和1.0电子伏特之间 eV），第一电极和第二电极之间的金属氧化物层，金属氧化物层使用体积介导的开关进行开关，并且具有大于4eV的带隙，并且存储元件从低电阻状态切换到高电阻 状态，反之亦然。

公开(公告)号：US20100243983A1

公开(公告)日：2010-09-30

申请号：US12610131

申请日：2009-10-30

申请人： Tony Chiang ,  Michael Miller ,  Prashant Phatak

发明人： Tony Chiang ,  Michael Miller ,  Prashant Phatak

IPC分类号： H01L47/00 ,  H01L21/16

CPC分类号： H01L45/122 ,  G11C13/0007 ,  G11C2213/32 ,  G11C2213/55 ,  G11C2213/56 ,  H01L21/265 ,  H01L21/322 ,  H01L27/2463 ,  H01L45/08 ,  H01L45/10 ,  H01L45/12 ,  H01L45/1233 ,  H01L45/1246 ,  H01L45/146 ,  H01L45/1616 ,  H01L45/1625 ,  H01L45/1641 ,  H01L45/165 ,  H01L45/1658 ,  H01L45/1675

摘要： Controlled localized defect paths for resistive memories are described, including a method for forming controlled localized defect paths including forming a first electrode forming a metal oxide layer on the first electrode, masking the metal oxide to create exposed regions and concealed regions of a surface of the metal oxide, and altering the exposed regions of the metal oxide to create localized defect paths beneath the exposed regions.

摘要翻译： 描述了用于电阻存储器的受控局部缺陷路径，包括用于形成受控局部缺陷路径的方法，包括形成在第一电极上形成金属氧化物层的第一电极，掩蔽金属氧化物以产生暴露区域和隐藏区域 金属氧化物，并且改变金属氧化物的暴露区域以在暴露区域下方产生局部缺陷路径。

公开(公告)号：US08502187B2

公开(公告)日：2013-08-06

申请号：US13454392

申请日：2012-04-24

申请人： Prashant Phatak ,  Tony Chiang ,  Michael Miller ,  Wen Wu

发明人： Prashant Phatak ,  Tony Chiang ,  Michael Miller ,  Wen Wu

IPC分类号： H01L47/00

CPC分类号： H01L45/1616 ,  H01L27/2409 ,  H01L27/2463 ,  H01L45/08 ,  H01L45/10 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/146

摘要： A resistive switching memory element including a doped silicon electrode is described, including a first electrode comprising doped silicon having a first work function, a second electrode having a second work function that is different from the first work function by between 0.1 and 1.0 electron volts (eV), a metal oxide layer between the first electrode and the second electrode, the metal oxide layer switches using bulk-mediated switching and has a bandgap of greater than 4 eV, and the memory element switches from a low resistance state to a high resistance state and vice versa.

摘要翻译： 描述了包括掺杂硅电极的电阻式开关存储元件，其包括包括具有第一功函数的掺杂硅的第一电极，具有与第一功函数不同的第二功函数的第二电极在0.1和1.0电子伏特之间 eV），第一电极和第二电极之间的金属氧化物层，金属氧化物层使用体积介导的开关进行开关，并且具有大于4eV的带隙，并且存储元件从低电阻状态切换到高电阻 状态，反之亦然。

公开(公告)号：US20120315725A1

公开(公告)日：2012-12-13

申请号：US13593116

申请日：2012-08-23

申请人： Michael Miller ,  Prashant Phatak ,  Tony Chiang ,  Xiyang Chen ,  April Schricker ,  Tanmay Kumar

发明人： Michael Miller ,  Prashant Phatak ,  Tony Chiang ,  Xiyang Chen ,  April Schricker ,  Tanmay Kumar

IPC分类号： H01L21/8239

CPC分类号： H01L45/16 ,  H01L21/265 ,  H01L21/31155 ,  H01L27/2463 ,  H01L29/8615 ,  H01L45/08 ,  H01L45/10 ,  H01L45/12 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/1608 ,  H01L45/1616 ,  H01L45/1625 ,  H01L45/1641 ,  H01L45/165

摘要： This disclosure provides a method of fabricating a semiconductor device layer and associated memory cell structures. By performing a surface treatment process (such as ion bombardment) of a semiconductor device layer to create defects having a deliberate depth profile, one may create multistable memory cells having more consistent electrical parameters. For example, in a resistive-switching memory cell, one may obtain a tighter distribution of set and reset voltages and lower forming voltage, leading to improved device yield and reliability. In at least one embodiment, the depth profile is selected to modulate the type of defects and their influence on electrical properties of a bombarded metal oxide layer and to enhance uniform defect distribution.

公开(公告)号：US20120305878A1

公开(公告)日：2012-12-06

申请号：US13149528

申请日：2011-05-31

申请人： Michael Miller ,  Prashant Phatak ,  Tony Chiang

发明人： Michael Miller ,  Prashant Phatak ,  Tony Chiang

IPC分类号： H01L45/00

CPC分类号： H01L45/085 ,  H01L27/2463 ,  H01L45/1233 ,  H01L45/1266 ,  H01L45/145 ,  H01L45/146

摘要： A nonvolatile memory element may include, but is not limited to: a first electrode; a second electrode; and a resistive switching material disposed between the first electrode and the second electrode, wherein at least one of the first electrode or the second electrode includes at least one of a metal cation or metalloid cation having a valence state, oxidation state or oxidation number and wherein the resistive switching material includes at least one of a metal cation or a metalloid cation having the same valence state oxidation state or oxidation number as the at least one of a metal cation or metalloid cation of the at least one of the first electrode or the second electrode.

摘要翻译： 非易失性存储元件可以包括但不限于：第一电极; 第二电极; 以及设置在第一电极和第二电极之间的电阻性开关材料，其中第一电极或第二电极中的至少一个包括具有价态，氧化态或氧化数的金属阳离子或准金属阳离子中的至少一种，并且其中 电阻开关材料包括与第一电极或第二电极中的至少一个的金属阳离子或准金属阳离子中的至少一种具有相同价态氧化态或氧化数的金属阳离子或准金属阳离子中的至少一种 电极。