公开(公告)号：US06934171B2

公开(公告)日：2005-08-23

申请号：US10672125

申请日：2003-09-26

申请人： Michael N. Dillon ,  Bret A. Oeltjen

发明人： Michael N. Dillon ,  Bret A. Oeltjen

IPC分类号： G05F1/40 ,  H02M1/00

CPC分类号： G05F1/40

摘要： An integrated circuit is provided, which includes first, second and third power supply conductors. The second power supply conductor has a higher voltage than the first power supply conductor, and the third power supply conductor has a higher voltage than the second power supply conductor. A high voltage power supply decoupling capacitor is coupled between the first and third power supply conductors. A low voltage power supply decoupling capacitor coupled between the first and second power supply conductors. A voltage reducer is coupled between the second and third power supply conductors. A plurality of semiconductor devices is biased between the first and second power supply conductors.

公开(公告)号：US06800882B2

公开(公告)日：2004-10-05

申请号：US10376837

申请日：2003-02-28

申请人： Michael N. Dillon ,  Bret A. Oeltjen

发明人： Michael N. Dillon ,  Bret A. Oeltjen

IPC分类号： H01L2710

CPC分类号： H01L27/0207 ,  H01L27/11807 ,  H03K3/356156 ,  Y10S257/903

摘要： A gate array integrated circuit is provided, which includes first and second voltage supply rails and a row of P-channel type transistors and adjacent N-channel type transistors located between first and second voltage supply rails. Adjacent ones of the P-channel and N-channel transistors have common control terminals. A multiple-bit memory cell is fabricated in the row and includes first and second latches, a read output, a first pass gate coupled between the first latch and the read output, and a second pass gate coupled between the second latch and the read output. The first pass gate includes a first one of the P-channel or N-channel transistors. The second pass gate includes a second one of the same type of the P-channel or N-channel transistors. The first and second same type transistors share a common diffusion region.

摘要翻译： 提供了一种门阵列集成电路，其包括位于第一和第二电压供应轨道之间的第一和第二电压供应轨道和一行P沟道型晶体管和相邻的N沟道型晶体管。 相邻的P沟道和N沟道晶体管具有公共控制端子。 在该行中制造多位存储器单元，并且包括第一和第二锁存器，读输出，耦合在第一锁存器和读输出之间的第一通过栅极以及耦合在第二锁存器和读输出端之间的第二通栅 。 第一通道门包括第一个P沟道或N沟道晶体管。 第二通道门包括相同类型的P沟道或N沟道晶体管中的第二通道。 第一和第二相同类型的晶体管共享公共扩散区域。

公开(公告)号：US07233540B1

公开(公告)日：2007-06-19

申请号：US11237059

申请日：2005-09-27

申请人： David Vinke ,  Bret A. Oeltjen ,  Michael N. Dillon

发明人： David Vinke ,  Bret A. Oeltjen ,  Michael N. Dillon

IPC分类号： G11C8/00

CPC分类号： G11C8/10 ,  G11C8/12 ,  G11C11/419

摘要： A disclosed memory, such as a random access memory (RAM) has multiple banks including a first bank and a second bank each having multiple latch cells configured to store data. The first bank has a first bit line, and the second bank has a second bit line. A first tri-state buffer has an input node coupled to the first bit line, an enable node coupled to receive a first enable signal, and an output node coupled to a tri-state bit line. A second tri-state buffer has an input node coupled to the second bit line, an enable node coupled to receive a second enable signal, and an output node coupled to the tri-state bit line. Enable signal generation logic uses a portion of an address signal to generate the first and second enable signals such that the first and second enable signals are not in an active state simultaneously. Avoiding concurrent activity of the enable signals eliminates contention on the tri-state output bit lines, and thereby prevents the mutually coupled tri-state bit lines output from the first and second tri-state buffers from being active at the same time. Placing a delay between activity minimizes contention on the mutually coupled, buffered bit line.

摘要翻译： 诸如随机存取存储器（RAM）的所公开的存储器具有包括第一存储体和第二存储体的多个存储体，每个存储体具有被配置为存储数据的多个锁存单元。 第一个银行有一个第一个位线，第二个银行有一个第二个位线。 第一三态缓冲器具有耦合到第一位线的输入节点，耦合以接收第一使能信号的使能节点和耦合到三态位线的输出节点。 第二三状态缓冲器具有耦合到第二位线的输入节点，耦合以接收第二使能信号的使能节点和耦合到三态位线的输出节点。 启用信号生成逻辑使用地址信号的一部分来产生第一和第二使能信号，使得第一和第二使能信号不同时处于活动状态。 避免使能信号的并行活动消除了对三态输出位线的争用，从而防止从第一和第二三态缓冲器输出的相互耦合的三态位线同时被激活。 在活动之间延迟最小化相互耦合的缓冲位线上的争用。

公开(公告)号：US07404154B1

公开(公告)日：2008-07-22

申请号：US11189026

申请日：2005-07-25

申请人： Ramnath Venkatraman ,  Michael N. Dillon ,  David A. Gardner ,  Carl Anthony Monzel, III ,  Subramanian Ramesh ,  Robert C. Armstrong ,  Gary Scott Delp ,  Scott Allen Peterson

发明人： Ramnath Venkatraman ,  Michael N. Dillon ,  David A. Gardner ,  Carl Anthony Monzel, III ,  Subramanian Ramesh ,  Robert C. Armstrong ,  Gary Scott Delp ,  Scott Allen Peterson

IPC分类号： G06F17/50

CPC分类号： H03K19/1735 ,  G06F2217/64 ,  H01L27/0207 ,  H01L27/11 ,  H01L27/1104 ,  H01L27/11807

摘要： A basic cell circuit architecture having plurality of cells with fixed transistors configurable for the formation of logic devices and/or single/dual port memory devices within a structured ASIC is provided. Different configurations of ensuing integrated circuits are achieved by forming variable interconnect layers above the fixed structures. The circuit architecture can achieve interconnection of transistors within a single cell and/or across multiple cells. The interconnection can be configured to form basic logic gates as well as more complex digital and analog subsystems. In addition, each cell contains a layout of transistors that can be variably coupled to achieve a memory device, such as a SRAM device. By having the capability of forming either a logic circuit element, a memory device, or both, the circuit architecture is both memory-centric and logic-centric, and more fully adaptable to modern-day SoCs.

摘要翻译： 提供了一种基本单元电路架构，其具有可配置用于形成结构化ASIC内的逻辑器件和/或单/双端口存储器件的固定晶体管的多个单元。 通过在固定结构上方形成可变互连层来实现随后的集成电路的不同配置。 电路架构可以实现单个电池内和/或跨多个电池的晶体管的互连。 互连可以配置成形成基本逻辑门，以及更复杂的数字和模拟子系统。 此外，每个单元包含可以可变地耦合以实现诸如SRAM器件的存储器件的晶体管的布局。 通过具有形成逻辑电路元件，存储器件或两者的能力，电路架构既是以内存为中心的，也是以逻辑为中心的，并且更完全适用于现代SoC。

公开(公告)号：US07760578B2

公开(公告)日：2010-07-20

申请号：US12254421

申请日：2008-10-20

申请人： David Vinke ,  Michael N. Dillon ,  Bret Alan Oeltjen ,  Uday Anumalachetty ,  Thomas Mathews Antisseril

发明人： David Vinke ,  Michael N. Dillon ,  Bret Alan Oeltjen ,  Uday Anumalachetty ,  Thomas Mathews Antisseril

IPC分类号： G11C5/14

CPC分类号： G11C5/063 ,  G11C8/10 ,  H01L2924/0002 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/00

摘要： An integrated circuit structure for distributing power to one or more standard cells in an integrated circuit includes a first plurality of standard cells and a power mesh power connection structure coupled to the cells. Each of the standard cells includes first and second power rails adapted for connection to a voltage supply and a voltage return, respectively, of the standard cells. Each standard cell in a subset of the standard cells is arranged in direct abutment with at least two other standard cells, and at least first and second end cells are arranged in direct abutment with at least one other standard cell of the first plurality of standard cells. The power mesh power connection structure includes a plurality of conductive elements formed in a plurality of different conductive layers in the integrated circuit. The power mesh power connection structure is operative to connect the first and second power rails of the first plurality of standard cells to the voltage supply and voltage return, respectively, and is configured so as to reduce a first voltage differential between respective first power rails of the standard cells and to reduce a second voltage differential between respective second power rails of the standard cells.

摘要翻译： 用于向集成电路中的一个或多个标准单元分配功率的集成电路结构包括耦合到该单元的第一多个标准单元和功率网格功率连接结构。 每个标准单元包括分别连接到标准单元的电压源和电压返回的第一和第二电源轨。 标准细胞子集中的每个标准细胞被布置成与至少两个其它标准细胞直接邻接，并且至少第一和第二末端细胞被布置成与第一多个标准细胞的至少一个其它标准细胞直接邻接 。 功率网格功率连接结构包括形成在集成电路中的多个不同导电层中的多个导电元件。 功率网格电力连接结构可操作以将第一多个标准单元的第一和第二电力轨分别连接到电压供应和电压返回，并且被配置为减少相应的第一电力轨之间的第一电压差 并且减小标准单元的相应的第二电源轨之间的第二电压差。

公开(公告)号：US06559701B1

公开(公告)日：2003-05-06

申请号：US09891648

申请日：2001-06-26

申请人： Michael N. Dillon

发明人： Michael N. Dillon

IPC分类号： G06F104

CPC分类号： G06F1/10

摘要： A method of reducing power rail transients on integrated circuits. The power rail transients are reduced by controlling clock skew in a manner which minimizes dI/dT current demands. The method provides that the phase of the clock to latches/flip flops is shifted in order to spread out the number of simultaneous switching elements. By controlling the number of simultaneous switching devices, a significant reduction in time rate of current demanded from the power rails can be achieved, thereby reducing the magnitude of VSS/VDD voltage transients due to parasitic inductances and resistances supplying power to the integrated circuit. Theoretically, the entire timing spread of the slack graph for clock skew can be used to control the number of simultaneous switching devices.

摘要翻译： 一种降低集成电路电源轨瞬变的方法。 通过以最小化dI / dT电流需求的方式控制时钟偏移来减少电源轨瞬变。 该方法提供了锁存/触发器的时钟相位被移位以便展开同时开关元件的数量。 通过控制同时开关装置的数量，可以实现从电源轨所需的电流的时间速度的显着降低，从而减小由寄生电感和向集成电路供电的电阻引起的VSS / VDD电压瞬变的幅度。 理论上，用于时钟偏移的松弛图的整个定时扩展可用于控制同时开关器件的数量。

公开(公告)号：US08166440B1

公开(公告)日：2012-04-24

申请号：US12139974

申请日：2008-06-16

申请人： Ramnath Venkatraman ,  Michael N. Dillon ,  David A. Gardner ,  Carl Anthony Monzel, III ,  Subramanian Ramesh ,  Robert C. Armstrong ,  Gary Scott Delp ,  Scott Allen Peterson

发明人： Ramnath Venkatraman ,  Michael N. Dillon ,  David A. Gardner ,  Carl Anthony Monzel, III ,  Subramanian Ramesh ,  Robert C. Armstrong ,  Gary Scott Delp ,  Scott Allen Peterson

IPC分类号： G06F17/50

CPC分类号： H03K19/1735 ,  G06F2217/64 ,  H01L27/0207 ,  H01L27/11 ,  H01L27/1104 ,  H01L27/11807

摘要： A basic cell circuit architecture having plurality of cells with fixed transistors configurable for the formation of logic devices and/or single/dual port memory devices within a structured ASIC is provided. Different configurations of ensuing integrated circuits are achieved by forming variable interconnect layers above the fixed structures. The circuit architecture can achieve interconnection of transistors within a single cell and/or across multiple cells. The interconnection can be configured to form basic logic gates as well as more complex digital and analog subsystems. In addition, each cell contains a layout of transistors that can be variably coupled to achieve a memory device, such as a SRAM device. By having the capability of forming either a logic circuit element, a memory device, or both, the circuit architecture is both memory-centric and logic-centric, and more fully adaptable to modern-day SoCs.

摘要翻译： 提供了一种基本单元电路架构，其具有可配置用于形成结构化ASIC内的逻辑器件和/或单/双端口存储器件的固定晶体管的多个单元。 通过在固定结构上方形成可变互连层来实现随后的集成电路的不同配置。 电路架构可以实现单个电池内和/或跨多个电池的晶体管的互连。 互连可以配置成形成基本逻辑门，以及更复杂的数字和模拟子系统。 此外，每个单元包含可以可变地耦合以实现诸如SRAM器件的存储器件的晶体管的布局。 通过具有形成逻辑电路元件，存储器件或两者的能力，电路架构既是以内存为中心的，也是以逻辑为中心的，并且更完全适用于现代SoC。

公开(公告)号：US07269803B2

公开(公告)日：2007-09-11

申请号：US10740284

申请日：2003-12-18

申请人： Khosro Khakzadi ,  Chris J. Tremel ,  Michael N. Dillon

发明人： Khosro Khakzadi ,  Chris J. Tremel ,  Michael N. Dillon

IPC分类号： G06F17/50 ,  H01L23/544

CPC分类号： G06F17/5072

摘要： A system and method for mapping Intellectual Property (IP) components onto a pre-fabricated chip slice allows a user to select a target location for placement of an IP component onto a slice. A slice definition of the pre-fabricated chip slice is searched for a legal location for the IP component that is near to the target location. The IP component is mapped to the legal location.

摘要翻译： 将知识产权（IP）组件映射到预制芯片片上的系统和方法允许用户选择用于将IP组件放置在片上的目标位置。 搜索预制芯片切片的切片定义，以获得靠近目标位置的IP组件的合法位置。 IP组件映射到合法位置。

公开(公告)号：US07231625B2

公开(公告)日：2007-06-12

申请号：US10952194

申请日：2004-09-28

申请人： Michael N. Dillon ,  Christopher J. Tremel

发明人： Michael N. Dillon ,  Christopher J. Tremel

IPC分类号： G06F17/50

CPC分类号： G06F17/5072

摘要： A method and apparatus are provided for placing cells in an integrated circuit layout pattern. A base layer layout pattern defines an array of base cell locations and base layer elements, wherein at least portions of some rows in the array are reserved for decoupling capacitor cells. Each decoupling capacitor cell has a width, which is greater than that of a single base cell location and which is abstracted from the base layer layout pattern. A cell library defines a plurality of cells, including a macro cell having open rows consistent with the rows in the base layer layout pattern that are reserved for the decoupling capacitor cells. The width of each decoupling capacitor cell is abstracted from the macro cell. Cells from the cell library, including the macro cell, are placed within a design layout pattern relative to the base layer layout pattern. An area consumed by the macro cell within the design layout pattern is independent of the width of the decoupling capacitor cells.

摘要翻译： 提供了一种用于将电池放置在集成电路布局图案中的方法和装置。 基层布局图形定义基本单元位置和基层元素的阵列，其中阵列中的一些行的至少部分被保留用于去耦合电容器单元。 每个去耦电容器单元的宽度大于单个基本单元位置的宽度，并且从基层布局图案中抽取出来。 单元库定义多个单元，包括具有与为去耦电容器单元保留的基层布局图案中的行一致的开放行的宏单元。 每个去耦电容器单元的宽度从宏单元中抽象出来。 来自细胞库的细胞（包括宏细胞）相对于基底层布局图案被放置在设计布局图案内。 设计布局图案内宏单元消耗的面积与去耦电容单元的宽度无关。

公开(公告)号：US07216323B2

公开(公告)日：2007-05-08

申请号：US10976518

申请日：2004-10-29

申请人： Michael N. Dillon ,  Christopher J. Tremel ,  Scott A. Peterson

发明人： Michael N. Dillon ,  Christopher J. Tremel ,  Scott A. Peterson

IPC分类号： G06F17/50

CPC分类号： G06F17/5068

摘要： Base platforms customizable into ICs are designed by identifying a plurality of macros for placement on the platform, each macro being defined in part by a plurality of elements that perform respective functions of the macro. Identical elements in a plurality of macros are identified, and a common element is placed on the platform for an identical element of at least two macros. All other elements of the macros are placed at locations on the platform relative to the common element as to satisfy macro placement rules for each macro. Identical elements can be identified by identifying similar elements in a plurality of macros, and creating a common element generic to the similar elements. The user designs a metalization layer to select macros and configure common elements to the selected macros.

摘要翻译： 通过识别用于放置在平台上的多个宏来设计可定制成IC的基本平台，每个宏部分地由执行宏的相应功能的多个元素定义。 识别多个宏中的相同元素，并且在平台上放置至少两个宏的相同元素的共同元素。 宏的所有其他元素相对于公共元素放置在平台上的位置，以满足每个宏的宏放置规则。 可以通过识别多个宏中的相似元素并创建通用于相似元素的公共元素来识别相同元素。 用户设计一个金属化层以选择宏并配置所选宏的公共元素。