利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

208 条记录 (耗时 0.021 秒)

    Oxidation method for altering a film structure and CMOS transistor structure formed therewith
    1.
    发明授权
    Oxidation method for altering a film structure and CMOS transistor structure formed therewith 失效
    用于改变由其形成的膜结构和CMOS晶体管结构的氧化方法

    公开(公告)号：US06982196B2

    公开(公告)日：2006-01-03

    申请号：US10605889

    申请日：2003-11-04

    申请人： Michael P. Belyansky ,  Diane C. Boyd ,  Bruce B. Doris ,  Oleg Gluschenkov

    发明人： Michael P. Belyansky ,  Diane C. Boyd ,  Bruce B. Doris ,  Oleg Gluschenkov

    IPC分类号： H01L21/8238

    CPC分类号： H01L29/7843 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/84 ,  H01L27/1203

    摘要： A structure and method are provided in which a stress present in a film is reduced in magnitude by oxidizing the film through atomic oxygen supplied to a surface of the film. In an embodiment, a mask is used to selectively block portions of the film so that the stress is relaxed only in areas exposed to the oxidation process. A structure and method are further provided in which a film having a stress is formed over source and drain regions of an NFET and a PFET. The stress present in the film over the source and drain regions of either the NFET or the PFET is then relaxed by oxidizing the film through exposure to atomic oxygen to provide enhanced mobility in at least one of the NFET or the PFET while maintaining desirable mobility in the other of the NFET and PFET.

    摘要翻译： 提供了一种结构和方法，其中通过供应到膜的表面的原子氧氧化膜来减小膜中存在的应力。 在一个实施例中，掩模用于选择性地阻挡膜的部分，使得应力仅在暴露于氧化过程的区域中松弛。 还提供了一种结构和方法，其中在NFET和PFET的源极和漏极区域上形成具有应力的膜。 然后在NFET或PFET的源极和漏极区域上存在于膜中的应力通过暴露于原子氧氧化膜而被松弛，以在至少一个NFET或PFET中提供增强的迁移率，同时保持理想的迁移率 另一个是NFET和PFET。

    Oxidation method for altering a film structure
    2.
    发明授权
    Oxidation method for altering a film structure 失效
    用于改变膜结构的氧化方法

    公开(公告)号：US07741166B2

    公开(公告)日：2010-06-22

    申请号：US11318818

    申请日：2005-12-27

    申请人： Michael P. Belyansky ,  Diane C. Boyd ,  Bruce B. Doris ,  Oleg Gluschenkov

    发明人： Michael P. Belyansky ,  Diane C. Boyd ,  Bruce B. Doris ,  Oleg Gluschenkov

    IPC分类号： H01L21/8238

    CPC分类号： H01L29/7843 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/84 ,  H01L27/1203

    摘要： A method is provided in which a stress present in a film is reduced in magnitude by oxidizing the film through atomic oxygen supplied to a surface of the film. In an embodiment, a mask is used to selectively block portions of the film so that the stress is relaxed only in areas exposed to the oxidation process. A method is further provided in which a film having a stress is formed over source and drain regions of an NFET and a PFET. The stress present in the film over the source and drain regions of either the NFET or the PFET is then relaxed by oxidizing the film through exposure to atomic oxygen to provide enhanced mobility in at least one of the NFET or the PFET while maintaining desirable mobility in the other of the NFET and PFET.

    摘要翻译： 提供了一种方法，其中通过供应到膜的表面的原子氧氧化膜来减小膜中存在的应力。 在一个实施例中，掩模用于选择性地阻挡膜的部分，使得应力仅在暴露于氧化过程的区域中松弛。 还提供了一种方法，其中在NFET和PFET的源极和漏极区域上形成具有应力的膜。 然后在NFET或PFET的源极和漏极区域上存在于膜中的应力通过暴露于原子氧氧化膜而被松弛，以在至少一个NFET或PFET中提供增强的迁移率，同时保持理想的迁移率 另一个是NFET和PFET。

    Method of forming self-aligned low-k gate cap
    3.
    发明授权
    Method of forming self-aligned low-k gate cap 失效
    形成自对准低k栅极帽的方法

    公开(公告)号：US07271049B2

    公开(公告)日：2007-09-18

    申请号：US11514605

    申请日：2006-09-01

    申请人： Oleg Gluschenkov ,  Jack A. Mandelman ,  Michael P. Belyansky ,  Bruce B. Doris

    发明人： Oleg Gluschenkov ,  Jack A. Mandelman ,  Michael P. Belyansky ,  Bruce B. Doris

    IPC分类号： H01L21/8238

    CPC分类号： H01L21/76834 ,  H01L21/28052 ,  H01L21/76897 ,  H01L29/6653 ,  H01L29/6659 ,  H01L29/7833

    摘要： A CMOS structure in which the gate-to-drain/source capacitance is reduced as well as various methods of fabricating such a structure are provided. In accordance with the present invention, it has been discovered that the gate-to-drain/source capacitance can be significantly reduced by forming a CMOS structure in which a low-k dielectric material is self-aligned with the gate conductor. A reduction in capacitance between the gate conductor and the contact via ranging from about 30% to greater than 40% has been seen with the inventive structures. Moreover, the total outer-fringe capacitance (gate to outer diffusion+gate to contact via) is reduced between 10-18%. The inventive CMOS structure includes at least one gate region including a gate conductor located a top a surface of a semiconductor substrate; and a low-k dielectric material that is self-aligned to the gate conductor.

    摘要翻译： 提供其中栅极 - 漏极/源极电容减小的CMOS结构以及制造这种结构的各种方法。 根据本发明，已经发现，通过形成其中低k电介质材料与栅极导体自对准的CMOS结构，可以显着降低栅 - 漏/源电容。 本发明的结构已经看到，栅极导体和接触孔之间的电容减小范围为约30％至大于40％。 此外，总外部电容（门到外部扩散+接触通孔的栅极）在10-18％之间降低。 本发明的CMOS结构包括至少一个栅极区，其包括位于半导体衬底的表面顶部的栅极导体; 以及与栅极导体自对准的低k电介质材料。

    Structure and method to improve channel mobility by gate electrode stress modification
    4.
    发明授权
    Structure and method to improve channel mobility by gate electrode stress modification 失效
    通过栅电极应力改变来提高沟道迁移率的结构和方法

    公开(公告)号：US07750410B2

    公开(公告)日：2010-07-06

    申请号：US11175223

    申请日：2005-07-07

    申请人： Michael P. Belyansky ,  Dureseti Chidambarrao ,  Omer H. Dokumaci ,  Bruce B. Doris ,  Oleg Gluschenkov

    发明人： Michael P. Belyansky ,  Dureseti Chidambarrao ,  Omer H. Dokumaci ,  Bruce B. Doris ,  Oleg Gluschenkov

    IPC分类号： H01L29/72

    CPC分类号： H01L29/7845 ,  H01L21/823807 ,  H01L21/823835 ,  H01L21/823842 ,  H01L29/4908 ,  H01L29/66795 ,  H01L29/785

    摘要： In producing complementary sets of metal-oxide-semiconductor (CMOS) field effect transistors, including nFET and pFET), carrier mobility is enhanced or otherwise regulated through the reacting the material of the gate electrode with a metal to produce a stressed alloy (preferably CoSi2, NiSi, or PdSi) within a transistor gate. In the case of both the nFET and pFET, the inherent stress of the respective alloy results in an opposite stress on the channel of respective transistor. By maintaining opposite stresses in the nFET and pFET alloys or silicides, both types of transistors on a single chip or substrate can achieve an enhanced carrier mobility, thereby improving the performance of CMOS devices and integrated circuits.

    摘要翻译： 在制造包括nFET和pFET的互补金属氧化物半导体（CMOS）场效应晶体管的情况下，通过使栅电极的材料与金属反应来增强或调节载流子迁移率，以产生应力合金（优选CoSi 2 ，NiSi或PdSi）。 在nFET和pFET两者的情况下，各合金的固有应力对相应晶体管的沟道产生相反的应力。 通过在nFET和pFET合金或硅化物中保持相反的应力，单个芯片或衬底上的两种类型的晶体管可实现增强的载流子迁移率，从而提高CMOS器件和集成电路的性能。

    Method of fabricating mobility enhanced CMOS devices
    5.
    发明授权
    Method of fabricating mobility enhanced CMOS devices 失效
    制造移动性增强型CMOS器件的方法

    公开(公告)号：US07205206B2

    公开(公告)日：2007-04-17

    申请号：US10708430

    申请日：2004-03-03

    申请人： Michael P. Belyansky ,  Bruce B. Doris ,  Oleg Gluschenkov

    发明人： Michael P. Belyansky ,  Bruce B. Doris ,  Oleg Gluschenkov

    IPC分类号： H01L21/76

    CPC分类号： H01L29/0653 ,  H01L29/66636 ,  H01L29/7848

    摘要： Compressive or tensile materials are selectively introduced beneath and in alignment with spacer areas and adjacent to channel areas of a semiconductor substrate to enhance or degrade electron and hole mobility in CMOS circuits. A process entails steps of creating dummy spacers, forming a dielectric mandrel (i.e., mask), removing the dummy spacers, etching recesses into the underlying semiconductor substrate, introducing a compressive or tensile material into a portion of each recess, and filling the remainder of each recess with substrate material.

    摘要翻译： 压缩或拉伸材料被选择性地引入到间隔区域的下方并且与半导体衬底的通道区域相邻并且与CMOS电路中的电子和空穴迁移率相关联。 一个过程需要创建虚拟间隔物的步骤，形成介质心轴（即掩模），去除虚拟间隔物，将凹槽蚀刻到下面的半导体衬底中，将压缩或拉伸材料引入每个凹部的一部分中， 每个凹槽与基底材料。

    Self-aligned low-k gate cap
    9.
    发明授权
    Self-aligned low-k gate cap 有权
    自对准低k门帽

    公开(公告)号：US07230296B2

    公开(公告)日：2007-06-12

    申请号：US10904391

    申请日：2004-11-08

    申请人： Oleg Gluschenkov ,  Jack A. Mandelman ,  Michael P. Belyansky ,  Bruce B. Doris

    发明人： Oleg Gluschenkov ,  Jack A. Mandelman ,  Michael P. Belyansky ,  Bruce B. Doris

    IPC分类号： H01L29/772

    CPC分类号： H01L21/76834 ,  H01L21/28052 ,  H01L21/76897 ,  H01L29/6653 ,  H01L29/6659 ,  H01L29/7833

    摘要： A CMOS structure in which the gate-to-drain/source capacitance is reduced as well as various methods of fabricating such a structure are provided. In accordance with the present invention, it has been discovered that the gate-to-drain/source capacitance can be significantly reduced by forming a CMOS structure in which a low-k dielectric material is self-aligned with the gate conductor. A reduction in capacitance between the gate conductor and the contact via ranging from about 30% to greater than 40% has been seen with the inventive structures. Moreover, the total outer-fringe capacitance (gate to outer diffusion+gate to contact via) is reduced between 10–18%. The inventive CMOS structure includes at least one gate region including a gate conductor located atop a surface of a semiconductor substrate; and a low-k dielectric material that is self-aligned to the gate conductor.

    摘要翻译： 提供其中栅极 - 漏极/源极电容减小的CMOS结构以及制造这种结构的各种方法。 根据本发明，已经发现，通过形成其中低k电介质材料与栅极导体自对准的CMOS结构，可以显着降低栅 - 漏/源电容。 本发明的结构已经看到，栅极导体和接触孔之间的电容减小范围为约30％至大于40％。 此外，总外部电容（门到外部扩散+接触通孔的栅极）在10-18％之间降低。 本发明的CMOS结构包括至少一个栅极区，其包括位于半导体衬底的表面上方的栅极导体; 以及与栅极导体自对准的低k电介质材料。

    CMOS transistor structure including film having reduced stress by exposure to atomic oxygen
    10.
    发明授权
    CMOS transistor structure including film having reduced stress by exposure to atomic oxygen 失效
    CMOS晶体管结构包括通过暴露于原子氧而具有减小的应力的膜

    公开(公告)号：US07202516B2

    公开(公告)日：2007-04-10

    申请号：US11318844

    申请日：2005-12-27

    申请人： Michael P. Belyansky ,  Diane C. Boyd ,  Bruce B. Doris ,  Oleg Gluschenkov

    发明人： Michael P. Belyansky ,  Diane C. Boyd ,  Bruce B. Doris ,  Oleg Gluschenkov

    IPC分类号： H01L29/80

    CPC分类号： H01L29/7843 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/84 ,  H01L27/1203

    摘要： A structure and method are provided in which a stress present in a film is reduced in magnitude by oxidizing the film through atomic oxygen supplied to a surface of the film. In an embodiment, a mask is used to selectively block portions of the film so that the stress is relaxed only in areas exposed to the oxidation process. A structure and method are further provided in which a film having a stress is formed over source and drain regions of an NFET and a PFET. The stress present in the film over the source and drain regions of either the NFET or the PFET is then relaxed by oxidizing the film through exposure to atomic oxygen to provide enhanced mobility in at least one of the NFET or the PFET while maintaining desirable mobility in the other of the NFET and PFET.

    摘要翻译： 提供了一种结构和方法，其中通过供应到膜的表面的原子氧氧化膜来减小膜中存在的应力。 在一个实施例中，掩模用于选择性地阻挡膜的部分，使得应力仅在暴露于氧化过程的区域中松弛。 还提供了一种结构和方法，其中在NFET和PFET的源极和漏极区域上形成具有应力的膜。 然后在NFET或PFET的源极和漏极区域上存在于膜中的应力通过暴露于原子氧氧化膜而被松弛，以在至少一个NFET或PFET中提供增强的迁移率，同时保持理想的迁移率 另一个是NFET和PFET。