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公开(公告)号：US07863646B2
公开(公告)日：2011-01-04
申请号：US11956043
申请日：2007-12-13
IPC分类号： H01L31/111 , H01L21/00
CPC分类号： H01L21/823807 , H01L27/092 , H01L29/7843
摘要： A transistor structure includes a first type of transistor (e.g., P-type) positioned in a first area of the substrate, and a second type of transistor (e.g., N-type) positioned in a second area of the substrate. A first type of stressing layer (compressive conformal nitride) is positioned above the first type of transistor and a second type of stressing layer (compressive tensile nitride) is positioned above the second type of transistor. In addition, another first type of stressing layer (compressive oxide) is positioned above the first type of transistor. Further, another second type of stressing layer (compressive oxide) is positioned above the second type of transistor.
摘要翻译： 晶体管结构包括位于衬底的第一区域中的第一类型的晶体管（例如，P型）和位于衬底的第二区域中的第二类型的晶体管（例如N型）。 第一类型的应力层（压缩共形氮化物）位于第一类型的晶体管上方，并且第二类型的应力层（压缩拉伸氮化物）位于第二类型晶体管之上。 此外，另一种第一类型的应力层（压缩氧化物）位于第一类型的晶体管之上。 此外，另一第二类型的应力层（压缩氧化物）位于第二类型晶体管的上方。
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公开(公告)号：US20090152638A1
公开(公告)日：2009-06-18
申请号：US11956043
申请日：2007-12-13
IPC分类号： H01L27/092
CPC分类号： H01L21/823807 , H01L27/092 , H01L29/7843
摘要： A transistor structure includes a first type of transistor (e.g., P-type) positioned in a first area of the substrate, and a second type of transistor (e.g., N-type) positioned in a second area of the substrate. A first type of stressing layer (compressive conformal nitride) is positioned above the first type of transistor and a second type of stressing layer (compressive tensile nitride) is positioned above the second type of transistor. In addition, another first type of stressing layer (compressive oxide) is positioned above the first type of transistor. Further, another second type of stressing layer (compressive oxide) is positioned above the second type of transistor.
摘要翻译： 晶体管结构包括位于衬底的第一区域中的第一类型的晶体管（例如，P型）和位于衬底的第二区域中的第二类型的晶体管（例如N型）。 第一类型的应力层（压缩共形氮化物）位于第一类型的晶体管上方，并且第二类型的应力层（压缩拉伸氮化物）位于第二类型晶体管之上。 此外，另一种第一类型的应力层（压缩氧化物）位于第一类型的晶体管之上。 此外，另一第二类型的应力层（压缩氧化物）位于第二类型晶体管的上方。
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3.发明申请COMPLEMENTARY FIELD EFFECT TRANSISTORS HAVING EMBEDDED SILICON SOURCE AND DRAIN REGIONS 有权具有嵌入式硅源和漏区的补充场效应晶体管公开(公告)号：US20090256173A1
公开(公告)日：2009-10-15
申请号：US12103301
申请日：2008-04-15
申请人： Xiangdong Chen , Thomas W. Dyer , Haining S. Yang
发明人： Xiangdong Chen , Thomas W. Dyer , Haining S. Yang
IPC分类号： H01L27/092 , H01L21/8238
CPC分类号： H01L21/823807 , H01L21/8258 , H01L29/1054 , H01L29/165 , H01L29/66636 , H01L29/7848
摘要： A method is provided of fabricating complementary stressed semiconductor devices, e.g., an NFET having a tensile stressed channel and a PFET having a compressive stressed channel. In such method, a first semiconductor region having a lattice constant larger than silicon can be epitaxially grown on an underlying semiconductor region of a substrate. The first semiconductor region can be grown laterally adjacent to a second semiconductor region which has a lattice constant smaller than that of silicon. Layers consisting essentially of silicon can be grown epitaxially onto exposed major surfaces of the first and second semiconductor regions after which gates can be formed which overlie the epitaxially grown silicon layers. Portions of the first and second semiconductor regions adjacent to the gates can be removed to form recesses. Regions consisting essentially of silicon can be grown within the recesses to form embedded silicon regions. Source and drain regions then can be formed in the embedded silicon regions. The difference between the lattice constant of silicon and that of the underlying first and second regions results in tensile stressed silicon over the first semiconductor region and compressive stressed silicon over the second semiconductor region.
摘要翻译： 提供了制造互补应力半导体器件的方法，例如具有拉伸应力通道的NFET和具有压应力通道的PFET。 在这种方法中，可以在衬底的下面的半导体区域外延生长具有大于硅的晶格常数的第一半导体区域。 第一半导体区域可以与具有比硅的晶格常数小的晶格常数的第二半导体区域横向生长。 基本上由硅组成的层可以外延生长到第一和第二半导体区域的暴露的主表面上，之后可以形成覆盖外延生长的硅层的栅极。 可以去除与栅极相邻的第一和第二半导体区域的部分以形成凹部。 基本上由硅组成的区域可以在凹槽内生长以形成嵌入的硅区域。 然后可以在嵌入的硅区域中形成源区和漏区。 硅的晶格常数和下面的第一和第二区域的晶格常数之间的差异导致第一半导体区域上的拉伸应力硅和第二半导体区域上的压应力硅。
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4.发明申请IMPROVED CMOS DEVICES WITH STRESSED CHANNEL REGIONS, AND METHODS FOR FABRICATING THE SAME 有权改进的具有应力通道区域的CMOS器件及其制造方法公开(公告)号：US20080001182A1
公开(公告)日：2008-01-03
申请号：US11427495
申请日：2006-06-29
IPC分类号： H01L29/76 , H01L27/148
CPC分类号： H01L29/7848 , H01L21/02532 , H01L21/30604 , H01L21/7624 , H01L21/823807 , H01L21/823878 , H01L21/84 , H01L27/092 , H01L27/1203 , H01L29/045 , H01L29/1054 , H01L29/16 , H01L29/161 , H01L29/165 , H01L29/66636 , H01L29/66772 , H01L29/78 , H01L29/78684 , H01L29/78696
摘要： The present invention relates to improved complementary metal-oxide-semiconductor (CMOS) devices with stressed channel regions. Specifically, each improved CMOS device comprises an field effect transistor (FET) having a channel region located in a semiconductor device structure, which has a top surface oriented along one of a first set of equivalent crystal planes and one or more additional surfaces oriented along a second, different set of equivalent crystal planes. Such additional surfaces can be readily formed by crystallographic etching. Further, one or more stressor layers with intrinsic compressive or tensile stress are located over the additional surfaces of the semiconductor device structure and are arranged and constructed to apply tensile or compressive stress to the channel region of the FET. Such stressor layers can be formed by pseudomorphic growth of a semiconductor material having a lattice constant different from the semiconductor device structure.
摘要翻译： 本发明涉及具有应力通道区域的改进的互补金属氧化物半导体（CMOS）器件。 具体地，每个改进的CMOS器件包括具有位于半导体器件结构中的沟道区的场效应晶体管（FET），其具有沿着第一组等效晶面中的一个取向的顶表面和沿着 第二，不同组的等效晶面。 这种附加表面可以通过晶体蚀刻容易地形成。 此外，具有固有压缩或拉伸应力的一个或多个应力层位于半导体器件结构的附加表面上，并且被布置和构造成将拉应力或压应力施加到FET的沟道区。 这样的应力层可以通过具有与半导体器件结构不同的晶格常数的半导体材料的假晶生长来形成。
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5.发明授权CMOS devices with stressed channel regions, and methods for fabricating the same 有权具有应力沟道区的CMOS器件及其制造方法公开(公告)号：US08853746B2
公开(公告)日：2014-10-07
申请号：US11427495
申请日：2006-06-29
IPC分类号： H01L29/76 , H01L27/148 , H01L29/66 , H01L29/165 , H01L29/786 , H01L29/78 , H01L27/12 , H01L21/84 , H01L29/04 , H01L29/10 , H01L21/762 , H01L21/8238
CPC分类号： H01L29/7848 , H01L21/02532 , H01L21/30604 , H01L21/7624 , H01L21/823807 , H01L21/823878 , H01L21/84 , H01L27/092 , H01L27/1203 , H01L29/045 , H01L29/1054 , H01L29/16 , H01L29/161 , H01L29/165 , H01L29/66636 , H01L29/66772 , H01L29/78 , H01L29/78684 , H01L29/78696
摘要： The present invention relates to improved complementary metal-oxide-semiconductor (CMOS) devices with stressed channel regions. Specifically, each improved CMOS device comprises an field effect transistor (FET) having a channel region located in a semiconductor device structure, which has a top surface oriented along one of a first set of equivalent crystal planes and one or more additional surfaces oriented along a second, different set of equivalent crystal planes. Such additional surfaces can be readily formed by crystallographic etching. Further, one or more stressor layers with intrinsic compressive or tensile stress are located over the additional surfaces of the semiconductor device structure and are arranged and constructed to apply tensile or compressive stress to the channel region of the FET. Such stressor layers can be formed by pseudomorphic growth of a semiconductor material having a lattice constant different from the semiconductor device structure.
摘要翻译： 本发明涉及具有应力通道区域的改进的互补金属氧化物半导体（CMOS）器件。 具体地，每个改进的CMOS器件包括具有位于半导体器件结构中的沟道区的场效应晶体管（FET），其具有沿着第一组等效晶面中的一个取向的顶表面和沿着 第二，不同组的等效晶面。 这种附加表面可以通过晶体蚀刻容易地形成。 此外，具有固有压缩或拉伸应力的一个或多个应力层位于半导体器件结构的附加表面上，并且被布置和构造成将拉应力或压应力施加到FET的沟道区。 这种应力层可以通过具有与半导体器件结构不同的晶格常数的半导体材料的假晶生长来形成。
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6.发明授权Complementary field effect transistors having embedded silicon source and drain regions 有权具有嵌入式硅源极和漏极区域的互补场效应晶体管公开(公告)号：US07968910B2
公开(公告)日：2011-06-28
申请号：US12103301
申请日：2008-04-15
申请人： Xiangdong Chen , Thomas W. Dyer , Haining S. Yang
发明人： Xiangdong Chen , Thomas W. Dyer , Haining S. Yang
CPC分类号： H01L21/823807 , H01L21/8258 , H01L29/1054 , H01L29/165 , H01L29/66636 , H01L29/7848
摘要： A method is provided of fabricating complementary stressed semiconductor devices, e.g., an NFET having a tensile stressed channel and a PFET having a compressive stressed channel. In such method, a first semiconductor region having a lattice constant larger than silicon can be epitaxially grown on an underlying semiconductor region of a substrate. The first semiconductor region can be grown laterally adjacent to a second semiconductor region which has a lattice constant smaller than that of silicon. Layers consisting essentially of silicon can be grown epitaxially onto exposed major surfaces of the first and second semiconductor regions after which gates can be formed which overlie the epitaxially grown silicon layers. Portions of the first and second semiconductor regions adjacent to the gates can be removed to form recesses. Regions consisting essentially of silicon can be grown within the recesses to form embedded silicon regions. Source and drain regions then can be formed in the embedded silicon regions. The difference between the lattice constant of silicon and that of the underlying first and second regions results in tensile stressed silicon over the first semiconductor region and compressive stressed silicon over the second semiconductor region.
摘要翻译： 提供了制造互补应力半导体器件的方法，例如具有拉伸应力通道的NFET和具有压应力通道的PFET。 在这种方法中，可以在衬底的下面的半导体区域外延生长具有大于硅的晶格常数的第一半导体区域。 第一半导体区域可以与具有比硅的晶格常数小的晶格常数的第二半导体区域横向生长。 基本上由硅组成的层可以外延生长到第一和第二半导体区域的暴露的主表面上，之后可以形成覆盖外延生长的硅层的栅极。 可以去除与栅极相邻的第一和第二半导体区域的部分以形成凹部。 基本上由硅组成的区域可以在凹槽内生长以形成嵌入的硅区域。 然后可以在嵌入的硅区域中形成源区和漏区。 硅的晶格常数和下面的第一和第二区域的晶格常数之间的差异导致第一半导体区域上的拉伸应力硅和第二半导体区域上的压应力硅。
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7.发明授权CMOS devices with hybrid channel orientations and method for fabricating the same 有权具有混合信道取向的CMOS器件及其制造方法公开(公告)号：US07736966B2
公开(公告)日：2010-06-15
申请号：US11968479
申请日：2008-01-02
IPC分类号： H01L21/8238
CPC分类号： H01L21/823807 , H01L21/82385 , H01L21/823857
摘要： The present invention relates to a method of fabricating a semiconductor substrate that includes forming at least first and second device regions, wherein the first device region includes a first recess having interior surfaces oriented along a first set of equivalent crystal planes, and wherein the second device region includes a second recess having interior surfaces oriented along a second, different set of equivalent crystal planes. The semiconductor device structure formed using such a semiconductor substrate includes at least one n-channel field effect transistor (n-FET) formed at the first device region having a channel that extends along the interior surfaces of the first recess, and at least one p-channel field effect transistor (p-FET) formed at the second device region having a channel that extends along the interior surfaces of the second recess.
摘要翻译： 本发明涉及一种制造半导体衬底的方法，该方法包括形成至少第一和第二器件区域，其中第一器件区域包括具有沿第一组等效晶面取向的内表面的第一凹槽，并且其中第二器件 区域包括具有沿着第二不同组的等效晶面取向的内表面的第二凹部。 使用这种半导体衬底形成的半导体器件结构包括形成在第一器件区域处的至少一个n沟道场效应晶体管（n-FET），其具有沿着第一凹部的内表面延伸的沟道，并且至少一个p - 沟道场效应晶体管（p-FET），其形成在具有沿着第二凹部的内表面延伸的沟道的第二器件区域处。
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8.发明授权CMOS devices with hybrid channel orientations and method for fabricating the same 有权具有混合信道取向的CMOS器件及其制造方法公开(公告)号：US07456450B2
公开(公告)日：2008-11-25
申请号：US11307481
申请日：2006-02-09
IPC分类号： H01L29/04
CPC分类号： H01L21/823807 , H01L21/82385 , H01L21/823857
摘要： The present invention relates to a semiconductor substrate comprising at least first and second device regions, wherein the first device region comprises a first recess having interior surfaces oriented along a first set of equivalent crystal planes, and wherein the second device region comprises a second recess having interior surfaces oriented along a second, different set of equivalent crystal planes. A semiconductor device structure can be formed using such a semiconductor substrate. Specifically, at least one n-channel field effect transistor (n-FET) can be formed at the first device region, which comprises a channel that extends along the interior surfaces of the first recess. At least one p-channel field effect transistor (p-FET) can be formed at the second device region, which comprises a channel that extends along the interior surfaces of the second recess.
摘要翻译： 本发明涉及包括至少第一和第二器件区域的半导体衬底，其中第一器件区域包括具有沿着第一组等效晶面取向的内表面的第一凹槽，并且其中第二器件区域包括第二凹部， 沿着第二不同组的等效晶面取向的内表面。 可以使用这种半导体衬底形成半导体器件结构。 具体而言，可以在第一器件区域形成至少一个n沟道场效应晶体管（n-FET），该第一器件区域包括沿着第一凹槽的内表面延伸的沟道。 至少一个p沟道场效应晶体管（p-FET）可以在第二器件区域形成，该第二器件区域包括沿着第二凹槽的内表面延伸的沟道。
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公开(公告)号：US08159031B2
公开(公告)日：2012-04-17
申请号：US12709873
申请日：2010-02-22
申请人： Thomas W. Dyer , Zhijiong Luo , Haining S. Yang
发明人： Thomas W. Dyer , Zhijiong Luo , Haining S. Yang
IPC分类号： H01L27/12
CPC分类号： H01L29/0653 , H01L21/76243 , H01L21/76267 , H01L21/76283 , H01L21/823481 , H01L21/823878 , H01L21/84 , H01L27/1203
摘要： An improved semiconductor-on-insulator (SOI) substrate is provided, which contains a patterned buried insulator layer at varying depths. Specifically, the SOI substrate has a substantially planar upper surface and comprises: (1) first regions that do not contain any buried insulator, (2) second regions that contain first portions of the patterned buried insulator layer at a first depth (i.e., measured from the planar upper surface of the SOI substrate), and (3) third regions that contain second portions of the patterned buried insulator layer at a second depth, where the first depth is larger than the second depth. One or more field effect transistors (FETs) can be formed in the SOI substrate. For example, the FETs may comprise: channel regions in the first regions of the SOI substrate, source and drain regions in the second regions of the SOI substrate, and source/drain extension regions in the third regions of the SOI substrate.
摘要翻译： 提供了一种改进的绝缘体上半导体（SOI）衬底，其包含在不同深度处的图案化掩埋绝缘体层。 具体而言，SOI衬底具有基本平坦的上表面，并且包括：（1）不包含任何埋入绝缘体的第一区域，（2）第一区域，其包含第一深度处的图案化掩埋绝缘体层的第一部分 从SOI衬底的平坦的上表面），和（3）第二深度大于第二深度的第二深度上包含图案化的掩埋绝缘体层的第二部分的第三区域。 可以在SOI衬底中形成一个或多个场效应晶体管（FET）。 例如，FET可以包括：SOI衬底的第一区域中的沟道区域，SOI衬底的第二区域中的源极和漏极区域以及SOI衬底的第三区域中的源极/漏极延伸区域。
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10.发明授权High performance 3D FET structures, and methods for forming the same using preferential crystallographic etching 有权高性能3D FET结构，以及使用优先晶体蚀刻形成相同方法公开(公告)号：US07884448B2
公开(公告)日：2011-02-08
申请号：US12500396
申请日：2009-07-09
申请人： Thomas W. Dyer , Haining S. Yang
发明人： Thomas W. Dyer , Haining S. Yang
IPC分类号： H01L29/04
CPC分类号： H01L21/823807 , H01L21/823821 , H01L27/0922 , H01L27/1211 , H01L29/04 , H01L29/66795 , H01L29/7853
摘要： The present invention relates to high performance three-dimensional (3D) field effect transistors (FETs). Specifically, a 3D semiconductor structure having a bottom surface oriented along one of a first set of equivalent crystal planes and multiple additional surfaces oriented along a second, different set of equivalent crystal planes can be used to form a high performance 3D FET with carrier channels oriented along the second, different set of equivalent crystal planes. More importantly, such a 3D semiconductor structure can be readily formed over the same substrate with an additional 3D semiconductor structure having a bottom surface and multiple additional surfaces all oriented along the first set of equivalent crystal planes. The additional 3D semiconductor structure can be used to form an additional 3D FET, which is complementary to the above-described 3D FET and has carrier channels oriented along the first set of equivalent crystal planes.
摘要翻译： 本发明涉及高性能三维（3D）场效应晶体管（FET）。 具体而言，可以使用具有沿着第一组等效晶面中的一个取向的底表面和沿着第二不同组的等效晶面取向的多个附加表面的3D半导体结构，以形成具有载体通道定向的高性能3D FET 沿着第二个不同组的等效晶面。 更重要的是，这种3D半导体结构可以容易地在具有底表面和多个附加表面的附加3D半导体结构的同一衬底上形成，所述另外的三维半导体结构全部沿着第一组等效晶面取向。 附加的3D半导体结构可以用于形成附加的3D FET，其与上述3D FET互补，并且具有沿着第一组等效晶面取向的载流子通道。
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