公开(公告)号：US5926831A

公开(公告)日：1999-07-20

申请号：US731350

申请日：1996-10-11

申请人： Juan Guillermo Revilla ,  Thomas Andrew Sartorius ,  Mark Michael Schaffer ,  James N. Dieffenderfer

发明人： Juan Guillermo Revilla ,  Thomas Andrew Sartorius ,  Mark Michael Schaffer ,  James N. Dieffenderfer

IPC分类号： G06F12/02 ,  G06F12/08

CPC分类号： G06F12/0215

摘要： A dynamically configured memory controller to prevent speculative memory accesses of non-well behaved memory. Such dynamic configuration of a memory controller may be accomplished by providing to the memory controller guard information associated with memory requests. The memory controller may then prevent speculative memory accesses when the guard information indicates that the memory requests are of non-well behaved memory. The guard information provided to the memory controller may include guard information associated with each memory request provided to the memory controller.

摘要翻译： 一种动态配置的存储器控​​制器，用于防止对非良好行为内存的推测性内存访问。 可以通过向存储器控制器提供与存储器请求相关联的保护信息来实现存储器控制器的这种动态配置。 当保护信息指示存储器请求是非良好的存储器时，存储器控制器可以防止推测存储器访问。 提供给存储器控制器的保护信息可以包括与提供给存储器控制器的每个存储器请求相关联的保护信息。

公开(公告)号：US5884051A

公开(公告)日：1999-03-16

申请号：US874639

申请日：1997-06-13

申请人： Mark Michael Schaffer ,  James N. Dieffenderfer ,  Edward Hammond Green, III ,  Juan Guillermo Revilla

发明人： Mark Michael Schaffer ,  James N. Dieffenderfer ,  Edward Hammond Green, III ,  Juan Guillermo Revilla

IPC分类号： G06F13/364 ,  G06F13/18 ,  G06F13/362

CPC分类号： G06F13/364

摘要： Bus performance in a computer system having multiple devices accessing a common shared bus may be improved by providing a flexible bus arbiter. Bus access is controlled using a bus arbiter which is operationally connected to each of the devices. Each device has a fixed programmable priority level and a dynamic priority level associated with it. The dynamic priority level comprises an arbiter dynamic priority level and a master dynamic priority level. Access to the bus by a device is controlled based on the combination of the programmable fixed priority level and the dynamic priority level associated with each device. While the programmable fixed priority level and the arbiter dynamic priority level as set by the arbiter are not controlled by the master, the master dynamic priority level is controlled by the master. If master dynamic priority is enabled, it overrides the arbiter dynamic priority level. If master dynamic priority is not enabled but arbiter dynamic priority is enabled, master dynamic priority overrides the programmable fixed priority level.

摘要翻译： 可以通过提供灵活的总线仲裁器来改进具有访问公共共享总线的多个设备的计算机系统中的总线性能。 总线访问使用总线仲裁器进行控制，总线仲裁器可操作地连接到每个设备。 每个设备具有固定的可编程优先级和与之相关联的动态优先级。 动态优先级包括仲裁器动态优先级和主动态优先级。 基于可编程固定优先级与与每个设备相关联的动态优先级的组合来控制设备对总线的访问。 虽然由仲裁器设置的可编程固定优先级和仲裁器动态优先级不受主控制，主动态优先级由主控制。 如果启用主动态优先级，它将覆盖仲裁器动态优先级。 如果未启用主动态优先级，但启用仲裁动态优先级，则主动态优先级将覆盖可编程固定优先级。

公开(公告)号：US5925118A

公开(公告)日：1999-07-20

申请号：US729555

申请日：1996-10-11

申请人： Juan Guillermo Revilla ,  Thomas Andrew Sartorius ,  Mark Michael Schaffer

发明人： Juan Guillermo Revilla ,  Thomas Andrew Sartorius ,  Mark Michael Schaffer

IPC分类号： G06F13/364 ,  G06F13/14

CPC分类号： G06F13/364

摘要： A communication system and method of communicating including a slave function connected to a master function by a single address bus, a write data bus and a read data bus so as to allow for overlapping multiple cycle read and write operations between the master function and the slave function. Preferably the communication system includes a plurality of slave functions connected to a master function by the single address bus, the write data bus and the read data bus. A plurality of master functions may be connected to the slave functions through a bus arbiter connected to the plurality of master functions by an address bus, a write data bus and a read data bus for each master function. The bus arbiter receives requests for communication operations from the plurality of master functions and selectively transmits the communication operations to the slave functions. In a preferred embodiment of the present invention, the master function and the slave function are further connected by a plurality of transfer qualifier signals which may specify whether the operation is a read or a write operation, the size of the transfer, the direction of the transfer or the type of transfer so as to further facilitate multiple cycle transfers with a single address specified on the single address bus.

摘要翻译： 通信系统和通信方法，其包括通过单个地址总线，写数据总线和读数据总线连接到主功能的从功能，以便允许在主功能和从机之间重叠多周期读和写操作 功能。 优选地，通信系统包括通过单个地址总线，写数据总线和读数据总线连接到主功能的多个从功能。 多个主功能可以通过总线仲裁器连接到从属功能，总线仲裁器通过地址总线，写数据总线和用于每个主功能的读数据总线连接到多个主功能。 总线仲裁器从多个主功能接收通信操作的请求，并且选择性地将通信操作发送到从属功能。 在本发明的优选实施例中，主功能和从功能还通过多个传输限定符信号进一步连接，传输限定符可以指定操作是读还是写操作，传输的大小，传输的方向 传输或传输类型，以便通过在单个地址总线上指定的单个地址来进一步促进多个周期传输。

公开(公告)号：US6081860A

公开(公告)日：2000-06-27

申请号：US975545

申请日：1997-11-20

申请人： Jeffrey Todd Bridges ,  Juan Guillermo Revilla ,  Thomas Andrew Sartorius ,  Mark Michael Schaffer

发明人： Jeffrey Todd Bridges ,  Juan Guillermo Revilla ,  Thomas Andrew Sartorius ,  Mark Michael Schaffer

IPC分类号： G06F13/364 ,  G06F13/00

CPC分类号： G06F13/364

摘要： A process and system for transferring data including at least one slave device connected to at least one master device through an arbiter device. The master and slave devices are connected by a single address bus, a write data bus and a read data bus. The arbiter device receives requests for data transfers from the master devices and selectively transmits the requests to the slave devices. The master devices and the slave devices are further connected by a plurality of transfer qualifier signals which may specify predetermined characteristics of the requested data transfers. Control signals are also communicated between the arbiter device and the slave devices to allow appropriate slave devices to latch addresses of requested second transfers during the pendency of current or primary data transfers so as to obviate an address transfer latency typically required for the second transfer. The design is configured to advantageously function in mixed systems which may include address-pipelining and non-address-pipelining slave devices.

摘要翻译： 一种用于传送数据的过程和系统，包括通过仲裁设备连接到至少一个主设备的至少一个从设备。 主设备和从设备通过单个地址总线，写数据总线和读数据总线连接。 仲裁设备接收来自主设备的数据传输请求，并选择性地将请求发送到从设备。 主设备和从设备通过可以指定所请求的数据传输的预定特性的多个传输限定符信号进一步连接。 控制信号也在仲裁设备和从设备之间通信，以允许适当的从设备在当前或主要数据传输的未决期间锁存所请求的第二传送的地址，以便消除通常为第二传送所需的地址传输等待时间。 该设计被配置为有利地在可以包括地址流水线和非地址流水线从设备的混合系统中起作用。

公开(公告)号：US5862353A

公开(公告)日：1999-01-19

申请号：US823736

申请日：1997-03-25

申请人： Juan Guillermo Revilla ,  Thomas Andrew Sartorius ,  Mark Michael Schaffer

发明人： Juan Guillermo Revilla ,  Thomas Andrew Sartorius ,  Mark Michael Schaffer

IPC分类号： G06F13/362 ,  G06F13/364 ,  G06F13/372 ,  G06F13/36

CPC分类号： G06F13/364

摘要： Bus performance in a computer system having multiple devices accessing a common shared bus may be improved by increasing throughput and decreasing latency while accounting for dynamic changes in bus usage. Devices submit a priority level along with a bus request to a bus controller. Upon receiving multiple requests, an arbiter of the bus controller compares the priority levels associated with the different bus requests and grants control of the bus to the device having the highest priority level. During each cycle that a device has control of the bus, a feedback logic circuit of the bus controller determines whether other bus requests are pending, and if so, determines the highest pending request priority level. Signals corresponding to the results of these determinations are fed back to each device. The device having control of the bus uses the combination of the currently pending request priority level and the device's own latency timer to determine whether it should maintain control of the bus or relinquish control of the bus.

摘要翻译： 具有访问公共共享总线的多个设备的计算机系统中的总线性能可以通过增加吞吐量和减少等待时间来改善，同时考虑总线使用的动态变化。 设备将总线请求提交给总线控制器。 在接收到多个请求时，总线控制器的仲裁器比较与不同总线请求相关联的优先级，并将总线的控制授权给具有最高优先级的设备。 在每个周期中，器件具有对总线的控制，总线控制器的反馈逻辑电路确定其他总线请求是否正在等待，如果是，则确定最高待机请求优先级。 与这些测定结果相对应的信号被反馈给每个设备。 具有总线控制的设备使用当前挂起的请求优先级和设备自身的延迟定时器的组合来确定其是否应该保持对总线的控制或放弃对总线的控制。

公开(公告)号：US06848041B2

公开(公告)日：2005-01-25

申请号：US10424961

申请日：2003-04-28

申请人： Gerald G. Pechanek ,  Edwin F. Barry ,  Juan Guillermo Revilla ,  Larry D. Larsen

发明人： Gerald G. Pechanek ,  Edwin F. Barry ,  Juan Guillermo Revilla ,  Larry D. Larsen

IPC分类号： G06F9/30 ,  G06F9/318 ,  G06F9/38 ,  G06F15/80

CPC分类号： G06F9/3822 ,  G06F9/30145 ,  G06F9/30149 ,  G06F9/30178 ,  G06F9/30181 ,  G06F9/382 ,  G06F9/3885

摘要： A hierarchical instruction set architecture (ISA) provides pluggable instruction set capability and support of array processors. The term pluggable is from the programmer's viewpoint and relates to groups of instructions that can easily be added to a processor architecture for code density and performance enhancements. One specific aspect addressed herein is the unique compacted instruction set which allows the programmer the ability to dynamically create a set of compacted instructions on a task by task basis for the primary purpose of improving control and parallel code density. These compacted instructions are parallelizable in that they are not specifically restricted to control code application but can be executed in the processing elements (PEs) in an array processor. The ManArray family of processors is designed for this dynamic compacted instruction set capability and also supports a scalable array of from one to N PEs. In addition, the ManArray ISA is defined as a hierarchy of ISAs which allows for future growth in instruction capability and supports the packing of multiple instructions within a hierarchy of instructions.

摘要翻译： 分层指令集架构（ISA）提供可插拔指令集功能和阵列处理器的支持。 术语pluggable来自程序员的观点，并且涉及可以容易地添加到处理器架构中以用于代码密度和性能增强的指令组。 本文所述的一个具体方面是独特的压缩指令集，其允许程序员能够通过任务为任务动态地创建一组压缩指令，以提高控制和并行代码密度的主要目的。 这些压缩指令是可并行的，因为它们不特别地限于控制代码应用，而是可以在阵列处理器中的处理元件（PE）中执行。 ManArray系列处理器专为此动态压缩指令集功能而设计，并且还支持从一个到N个PE的可扩展阵列。 此外，ManArray ISA被定义为ISA的层次结构，其允许未来指令能力的增长并且支持在指令层次结构内的多个指令的打包。

公开(公告)号：US06446191B1

公开(公告)日：2002-09-03

申请号：US09677732

申请日：2000-10-02

申请人： Gerald G. Pechanek ,  Thomas L. Drabenstott ,  Juan Guillermo Revilla ,  David Carl Strube ,  Grayson Morris

发明人： Gerald G. Pechanek ,  Thomas L. Drabenstott ,  Juan Guillermo Revilla ,  David Carl Strube ,  Grayson Morris

IPC分类号： G06F1516

CPC分类号： G06F9/30145 ,  G06F9/30167 ,  G06F9/3802 ,  G06F9/3853 ,  G06F9/3885 ,  G06F9/3887 ,  G06F9/3889

摘要： A SIMD machine employing a plurality of parallel processor (PEs) in which communications hazards are eliminated in an efficient manner. An indirect Very Long Instruction Word instruction memory (VIM) is employed along with execute and delimiter instructions. A masking mechanism may be employed to control which PEs have their VIMs loaded. Further, a receive model of operation is preferably employed. In one aspect, each PE operates to control a switch that selects from which PE it receives. The present invention addresses a better machine organization for execution of parallel algorithms that reduces hardware cost and complexity while maintaining the best characteristics of both SIMD and MIMD machines and minimizing communication latency. This invention brings a level of MIMD computational autonomy to SIMD indirect Very Long Instruction Word (iVLIW) processing elements while maintaining the single thread of control used in the SIMD machine organization. Consequently, the term Synchronous-MIMD (SMIMD) is used to describe the present approach.

摘要翻译： 使用多个并行处理器（PE）的SIMD机器，其中以有效的方式消除通信危险。 使用间接超长指令字指令存储器（VIM）以及执行和分隔符指令。 可以使用掩蔽机制来控制哪些PE装载有VIM。 此外，优选采用操作的接收模式。 在一个方面，每个PE操作以控制从其接收的PE选择的交换机。 本发明解决了用于执行并行算法的更好的机器组织，其降低硬件成本和复杂性，同时保持SIMD和MIMD机器的最佳特性并最小化通信延迟。 本发明为SIMD间接超长指令字（iVLIW）处理元件提供了MIMD计算自主性水平，同时保持了SIMD机器组织中使用的单一线程控制。 因此，术语Synchronous-MIMD（SMIMD）用于描述当前的方法。

公开(公告)号：USRE41703E1

公开(公告)日：2010-09-14

申请号：US10872995

申请日：2004-06-21

申请人： Gerald George Pechanek ,  Thomas L. Drabenstott ,  Juan Guillermo Revilla ,  David Strube ,  Grayson Morris

发明人： Gerald George Pechanek ,  Thomas L. Drabenstott ,  Juan Guillermo Revilla ,  David Strube ,  Grayson Morris

IPC分类号： G06F15/16

CPC分类号： G06F9/30145 ,  G06F9/30167 ,  G06F9/3802 ,  G06F9/3853 ,  G06F9/3885 ,  G06F9/3887 ,  G06F9/3889

摘要： A SIMD machine employing a plurality of parallel processor (PEs) in which communications hazards are eliminated in an efficient manner. An indirect Very Long Instruction Word instruction memory (VIM) is employed along with execute and delimiter instructions. A masking mechanism may be employed to control which PEs have their VIMs loaded. Further, a receive model of operation is preferably employed. In one aspect, each PE operates to control a switch that selects from which PE it receives. The present invention addresses a better machine organization for execution of parallel algorithms that reduces hardware cost and complexity while maintaining the best characteristics of both SIMD and MIMD machines and minimizing communication latency. This invention brings a level of MIMD computational autonomy to SIMD indirect Very Long Instruction Word (iVLIW) processing elements while maintaining the single thread of control used in the SIMD machine organization. Consequently, the term Synchronous-MIMD (SMIMD) is used to describe the present approach.

摘要翻译： 使用多个并行处理器（PE）的SIMD机器，其中以有效的方式消除通信危险。 使用间接超长指令字指令存储器（VIM）以及执行和分隔符指令。 可以使用掩蔽机制来控制哪些PE装载有VIM。 此外，优选采用操作的接收模式。 在一个方面，每个PE操作以控制从其接收的PE选择的交换机。 本发明解决了用于执行并行算法的更好的机器组织，其降低硬件成本和复杂性，同时保持SIMD和MIMD机器的最佳特性并最小化通信延迟。 本发明为SIMD间接超长指令字（iVLIW）处理元件提供了MIMD计算自主性水平，同时保持了SIMD机器组织中使用的单一线程控制。 因此，术语Synchronous-MIMD（SMIMD）用于描述当前的方法。

公开(公告)号：US06216223B1

公开(公告)日：2001-04-10

申请号：US09228374

申请日：1999-01-12

申请人： Juan Guillermo Revilla ,  Edwin F. Barry ,  Patrick Rene Marchand ,  Gerald G. Pechanek

发明人： Juan Guillermo Revilla ,  Edwin F. Barry ,  Patrick Rene Marchand ,  Gerald G. Pechanek

IPC分类号： G06F922

CPC分类号： G06F9/3873 ,  G06F9/30058 ,  G06F9/30076 ,  G06F9/30079 ,  G06F9/30181 ,  G06F9/30189 ,  G06F9/3802 ,  G06F9/3842 ,  G06F9/3853 ,  G06F9/3859 ,  G06F9/3867 ,  G06F9/3885

摘要： A ManArray processor pipeline design addresses an indirect VLIW memory access problem without increasing branch latency by providing a dynamically reconfigurable instruction pipeline for SIWs requiring a VLIW to be fetched. By introducing an additional cycle in the pipeline only when a VLIW fetch is required, the present invention solves the VLIW memory access problem. The pipeline stays in an expanded state, in general, until a branch type or load VLIW memory type operation is detected returning the pipeline to a compressed pipeline operation. By compressing the pipeline when a branch type operation is detected, the need for an additional cycle for the branch operation is avoided. Consequently, the shorter compressed pipeline provides more efficient performance for branch intensive control code as compared to a fixed pipeline with an expanded number of pipeline stages. In addition, the dynamic reconfigurable pipeline is scalable allowing each processing element (PE) in an array of PEs to expand and compress the pipeline in synchronism allowing iVLIW operations to execute independently in each PE. This is accomplished by having distributed pipelines in operation in parallel, one in each PE and in the controller sequence processor (SP).

摘要翻译： ManArray处理器管线设计通过为需要获取VLIW的SIW提供动态可重配置的指令流水线来解决间接VLIW存储器访问问题，而不会增加分支延迟。 通过仅在需要VLIW提取时引入额外的循环，本发明解决了VLIW存储器访问问题。 通常，管线保持在扩展状态，直到检测到分支类型或负载VLIW存储器类型操作，将流水线返回到压缩管道操作。 当检测到分支类型操作时通过压缩流水线，避免了用于分支操作的附加周期的需要。 因此，与具有扩展数量的流水线级的固定管道相比，较短的压缩流水线为分支密集型控制代码提供了更高效的性能。 此外，动态可重配置流水线是可扩展的，允许PE阵列中的每个处理元件（PE）同步地扩展和压缩流水线，从而允许iVLIW操作在每个PE中独立执行。 这是通过并行运行分布式管道，每个PE中的一个和控制器序列处理器（SP）中实现的。

公开(公告)号：US5689659A

公开(公告)日：1997-11-18

申请号：US550043

申请日：1995-10-30

申请人： Donald L. Tietjen ,  Frank C. Galloway ,  Juan Guillermo Revilla ,  Nancy G. Woodbridge ,  David M. Menard ,  Ronny L. Arnold

发明人： Donald L. Tietjen ,  Frank C. Galloway ,  Juan Guillermo Revilla ,  Nancy G. Woodbridge ,  David M. Menard ,  Ronny L. Arnold

IPC分类号： G06F13/28 ,  G06F13/40 ,  G06F13/00

CPC分类号： G06F13/28 ,  G06F13/4018

摘要： A data processing system (10) having a bus controller (5) that uses a communication bus (22) which adapts to various system resources (7) and is capable of burst transfers. In one embodiment, the processor core (2) and system resources (7) supply control signals supplying required parameters of the next transfer. The bus controller is capable of transferring operands and/or instructions in incremental bursts from these system resources. Each transfer data burst has an associated unique access address where successive bytes of data are associated with sequential addresses and the burst increment equals the data port size. The burst capability is dependent on the ability of system resource (7) to burst data and can be inhibited with a transfer burst inhibit signal. The length of the desired data is controlled by a sizing signal from the core (2) or from cache and the increment size is supplied by the resource (7).

摘要翻译： 一种具有总线控制器（5）的数据处理系统（10），该总线控制器（5）使用适应各种系统资源（7）并且能够进行突发传输的通信总线（22）。 在一个实施例中，处理器核心（2）和系统资源（7）提供提供下一个传输的所需参数的控制信号。 总线控制器能够以这些系统资源的增量突发传送操作数和/或指令。 每个传输数据脉冲串具有相关联的唯一访问地址，其中连续的数据字节与顺序地址相关联，并且突发增量等于数据端口大小。 突发能力取决于系统资源（7）突发数据的能力，并且可以用传输突发禁止信号来禁止。 所需数据的长度由来自核心（2）或高速缓存的大小调整信号控制，增量大小由资源（7）提供。