公开(公告)号：US5926831A

公开(公告)日：1999-07-20

申请号：US731350

申请日：1996-10-11

申请人： Juan Guillermo Revilla ,  Thomas Andrew Sartorius ,  Mark Michael Schaffer ,  James N. Dieffenderfer

发明人： Juan Guillermo Revilla ,  Thomas Andrew Sartorius ,  Mark Michael Schaffer ,  James N. Dieffenderfer

IPC分类号： G06F12/02 ,  G06F12/08

CPC分类号： G06F12/0215

摘要： A dynamically configured memory controller to prevent speculative memory accesses of non-well behaved memory. Such dynamic configuration of a memory controller may be accomplished by providing to the memory controller guard information associated with memory requests. The memory controller may then prevent speculative memory accesses when the guard information indicates that the memory requests are of non-well behaved memory. The guard information provided to the memory controller may include guard information associated with each memory request provided to the memory controller.

摘要翻译： 一种动态配置的存储器控​​制器，用于防止对非良好行为内存的推测性内存访问。 可以通过向存储器控制器提供与存储器请求相关联的保护信息来实现存储器控制器的这种动态配置。 当保护信息指示存储器请求是非良好的存储器时，存储器控制器可以防止推测存储器访问。 提供给存储器控制器的保护信息可以包括与提供给存储器控制器的每个存储器请求相关联的保护信息。

公开(公告)号：US5884051A

公开(公告)日：1999-03-16

申请号：US874639

申请日：1997-06-13

申请人： Mark Michael Schaffer ,  James N. Dieffenderfer ,  Edward Hammond Green, III ,  Juan Guillermo Revilla

发明人： Mark Michael Schaffer ,  James N. Dieffenderfer ,  Edward Hammond Green, III ,  Juan Guillermo Revilla

IPC分类号： G06F13/364 ,  G06F13/18 ,  G06F13/362

CPC分类号： G06F13/364

摘要： Bus performance in a computer system having multiple devices accessing a common shared bus may be improved by providing a flexible bus arbiter. Bus access is controlled using a bus arbiter which is operationally connected to each of the devices. Each device has a fixed programmable priority level and a dynamic priority level associated with it. The dynamic priority level comprises an arbiter dynamic priority level and a master dynamic priority level. Access to the bus by a device is controlled based on the combination of the programmable fixed priority level and the dynamic priority level associated with each device. While the programmable fixed priority level and the arbiter dynamic priority level as set by the arbiter are not controlled by the master, the master dynamic priority level is controlled by the master. If master dynamic priority is enabled, it overrides the arbiter dynamic priority level. If master dynamic priority is not enabled but arbiter dynamic priority is enabled, master dynamic priority overrides the programmable fixed priority level.

摘要翻译： 可以通过提供灵活的总线仲裁器来改进具有访问公共共享总线的多个设备的计算机系统中的总线性能。 总线访问使用总线仲裁器进行控制，总线仲裁器可操作地连接到每个设备。 每个设备具有固定的可编程优先级和与之相关联的动态优先级。 动态优先级包括仲裁器动态优先级和主动态优先级。 基于可编程固定优先级与与每个设备相关联的动态优先级的组合来控制设备对总线的访问。 虽然由仲裁器设置的可编程固定优先级和仲裁器动态优先级不受主控制，主动态优先级由主控制。 如果启用主动态优先级，它将覆盖仲裁器动态优先级。 如果未启用主动态优先级，但启用仲裁动态优先级，则主动态优先级将覆盖可编程固定优先级。

公开(公告)号：US06826747B1

公开(公告)日：2004-11-30

申请号：US09412124

申请日：1999-10-05

申请人： Victor Roberts Augsburg ,  Jeffrey Todd Bridges ,  Thomas K. Collopy ,  James N. Dieffenderfer ,  Thomas Andrew Sartorius

发明人： Victor Roberts Augsburg ,  Jeffrey Todd Bridges ,  Thomas K. Collopy ,  James N. Dieffenderfer ,  Thomas Andrew Sartorius

IPC分类号： G06F1130

CPC分类号： G06F11/3466

摘要： A system and method for tracing program code within a processor having an embedded cache memory. The non-invasive tracing technique minimizes the need for trace information to be broadcast externally. The tracing technique monitors changes in instruction flow from the normal execution stream of the code. The tracing technique monitors the updating of processor branch target register contents in order to monitor branch target flow of the code. Tracing of the program flow includes tracing instructions both before and after a trace triggering event. The implementation of periodic synchronizing events enables the tracing of instructions occurring before and after a triggering event, and then providing the trace information externally from the processor.

摘要翻译： 一种用于在具有嵌入式高速缓冲存储器的处理器内跟踪程序代码的系统和方法。 非侵入性跟踪技术最大限度地减少了要在外部广播的跟踪信息的需要。 跟踪技术监视来自代码的正常执行流的指令流程的变化。 跟踪技术监控处理器分支目标寄存器内容的更新，以便监视代码的分支目标流。 跟踪程序流程包括跟踪触发事件之前和之后的跟踪指令。 周期性同步事件的实现使得能够跟踪在触发事件之前和之后发生的指令，然后从处理器向外部提供跟踪信息。

公开(公告)号：US5910930A

公开(公告)日：1999-06-08

申请号：US868314

申请日：1997-06-03

申请人： James N. Dieffenderfer ,  George Filip Diniz ,  Thomas Andrew Sartorius

发明人： James N. Dieffenderfer ,  George Filip Diniz ,  Thomas Andrew Sartorius

IPC分类号： G06F1/32 ,  G04F5/00 ,  G06F1/00

CPC分类号： G06F1/3203

摘要： Method and apparatus for dynamic control of power management circuitry in a microprocessor. A clock and power management subsystem within the microprocessor contains clock generation and control logic and a powered-down mode register. The register is controlled by register control logic in the microprocessor and determines the powered-down mode of the various hardware units that make up the microprocessor. The clock generation and control logic also receives a powered-down mode enable signal from each of the hardware units. The hardware unit receive a re-power-up signal which, when activated and deactivated, can cause the hardware units to de-activate and activate, respectively, the powered-down mode enable signal. This combination of features allows continuous, repetitive, dynamic, hardware-controlled entry into exit from power saving modes without software intervention, thereby allowing the power saving modes to be used more often and more effectively for shorter periods of time than would be possible with software controlled power management.

摘要翻译： 用于微处理器中功率管理电路的动态控制的方法和装置。 微处理器内的时钟和电源管理子系统包含时钟生成和控制逻辑以及掉电模式寄存器。 寄存器由微处理器中的寄存器控制逻辑控制，并确定构成微处理器的各种硬件单元的掉电模式。 时钟生成和控制逻辑还从每个硬件单元接收掉电模式使能信号。 硬件单元接收重新上电信号，当被激活和去激活时，可以使硬件单元分别去激活和激活掉电模式使能信号。 这种功能的组合允许连续的，重复的，动态的，硬件控制的输入从省电模式退出而不需要软件干预，从而允许在比软件可能的更短的时间段内更频繁地使用节能模式 受控电源管理。

公开(公告)号：US5996092A

公开(公告)日：1999-11-30

申请号：US760553

申请日：1996-12-05

申请人： Victor Roberts Augsburg ,  Jeffrey Todd Bridges ,  Thomas K. Collopy ,  James N. Dieffenderfer ,  Thomas Andrew Sartorius

发明人： Victor Roberts Augsburg ,  Jeffrey Todd Bridges ,  Thomas K. Collopy ,  James N. Dieffenderfer ,  Thomas Andrew Sartorius

IPC分类号： G06F11/34 ,  G06F11/30

CPC分类号： G06F11/3466

摘要： A system and method for tracing program code within a processor having an embedded cache memory. The non-invasive tracing technique minimizes the need for trace information to be broadcast externally. The tracing technique monitors changes in instruction flow from the normal execution stream of the code. The tracing technique monitors the updating of processor branch target register contents in order to monitor branch target flow of the code. Tracing of the program flow includes tracing instructions both before and after a trace triggering event. The implementation of periodic synchronizing events enables the tracing of instructions occurring before and after a triggering event.

摘要翻译： 一种用于在具有嵌入式高速缓冲存储器的处理器内跟踪程序代码的系统和方法。 非侵入性跟踪技术最大限度地减少了要在外部广播的跟踪信息的需要。 跟踪技术监视来自代码的正常执行流的指令流程的变化。 跟踪技术监控处理器分支目标寄存器内容的更新，以便监视代码的分支目标流。 跟踪程序流程包括跟踪触发事件之前和之后的跟踪指令。 周期性同步事件的实现使得能够跟踪在触发事件之前和之后发生的指令。

公开(公告)号：US5809293A

公开(公告)日：1998-09-15

申请号：US283128

申请日：1994-07-29

申请人： Jeffrey Todd Bridges ,  Thomas K. Collopy ,  James N. Dieffenderfer ,  Thomas Joseph Irene ,  Harry I. Linzer ,  Thomas Andrew Sartorius

发明人： Jeffrey Todd Bridges ,  Thomas K. Collopy ,  James N. Dieffenderfer ,  Thomas Joseph Irene ,  Harry I. Linzer ,  Thomas Andrew Sartorius

IPC分类号： G06F11/34 ,  G06F11/36 ,  G06F9/00

CPC分类号： G06F11/3636 ,  G06F11/3466 ,  G06F11/3648 ,  G06F2201/865

摘要： A system and method for tracing program code within a processor having an embedded cache memory. The non-invasive tracing technique minimizes the need for trace information to be broadcast externally. The tracing technique monitors changes in instruction flow from the normal execution stream of the code. The tracing technique monitors the updating of processor branch target register contents in order to monitor branch target flow of the code. A FIFO and serial logic circuitry is utilized to minimize the number of chip pins required to broadcast the information from the chip. The tracing technique utilizes instruction and data breakpoint debug functions to signal an external trace tool that a trace event has occurred.

摘要翻译： 一种用于在具有嵌入式高速缓冲存储器的处理器内跟踪程序代码的系统和方法。 非侵入性跟踪技术最大限度地减少了要在外部广播的跟踪信息的需要。 跟踪技术监视来自代码的正常执行流的指令流程的变化。 跟踪技术监控处理器分支目标寄存器内容的更新，以便监视代码的分支目标流。 使用FIFO和串行逻辑电路来最小化从芯片广播信息所需的芯片引脚数。 跟踪技术利用指令和数据断点调试功能来发出跟踪事件发生的外部跟踪工具。

公开(公告)号：US5724572A

公开(公告)日：1998-03-03

申请号：US341789

申请日：1994-11-18

申请人： James N. Dieffenderfer ,  Harry I. Linzer ,  Thomas Andrew Sartorius

发明人： James N. Dieffenderfer ,  Harry I. Linzer ,  Thomas Andrew Sartorius

IPC分类号： G06F7/74 ,  G06F7/10

CPC分类号： G06F7/74 ,  Y10S707/99936

摘要： A method and apparatus for detecting the null byte at the end of a character string. The method and apparatus first logically concatenates two 32-bit input values into a single 64 bit value. Next, the 64-bit value is divided into 8 bytes. Then, a logical OR operation is performed on each byte and the results are put into an encoder. Finally, the encoder interprets the results of the OR operations and places output values into processor registers which indicate whether or where a null byte was detected.

摘要翻译： 一种用于检测字符串末尾的空字节的方法和装置。 该方法和设备首先将两个32位输入值逻辑级联为单个64位值。 接下来，64位值被分为8个字节。 然后，对每个字节执行逻辑或运算，并将结果放入编码器。 最后，编码器解释OR操作的结果，并将输出值放在处理器寄存器中，指示是否检测到空字节。

公开(公告)号：US20080177981A1

公开(公告)日：2008-07-24

申请号：US11868557

申请日：2007-10-08

申请人： James N. Dieffenderfer ,  Richard W. Doing ,  Brian M. Stempel ,  Steven R. Testa ,  Kenichi Tsuchiya

发明人： James N. Dieffenderfer ,  Richard W. Doing ,  Brian M. Stempel ,  Steven R. Testa ,  Kenichi Tsuchiya

IPC分类号： G06F9/30

CPC分类号： G06F9/3842 ,  G06F9/3861 ,  G06F9/3867

摘要： A method and apparatus for executing instructions in a pipeline processor. The method decreases the latency between an instruction cache and a pipeline processor when bubbles occur in the processing stream due to an execution of a branch correction, or when an interrupt changes the sequence of an instruction stream. The latency is reduced when a decode stage for detecting branch prediction and a related instruction queue location have invalid data representing a bubble in the processing stream. Instructions for execution are inserted in parallel into the decode stage and instruction queue, thereby reducing by one cycle time the length of the pipeline stage.

摘要翻译： 一种用于在流水线处理器中执行指令的方法和装置。 由于执行分支校正，或当中断改变指令流的序列时，该方法减少了在处理流中发生气泡时指令高速缓存和流水线处理器之间的等待时间。 当用于检测分支预测的解码级和相关指令队列位置具有表示处理流中的气泡的无效数据时，等待时间减少。 执行指令并行插入到解码级和指令队列中，从而将流水线级的长度减少一个周期。

公开(公告)号：US07395380B2

公开(公告)日：2008-07-01

申请号：US10393116

申请日：2003-03-20

申请人： James N. Dieffenderfer ,  Bernard C. Drerup ,  Jaya P. Ganasan ,  Richard G. Hofmann ,  Thomas A. Sartorius ,  Thomas P. Speier ,  Barry J. Wolford

发明人： James N. Dieffenderfer ,  Bernard C. Drerup ,  Jaya P. Ganasan ,  Richard G. Hofmann ,  Thomas A. Sartorius ,  Thomas P. Speier ,  Barry J. Wolford

IPC分类号： G06F12/00 ,  G06F3/00

CPC分类号： G06F12/0831 ,  Y02D10/13

摘要： A method and structure for snooping cache memories of several snooping masters connected to a bus macro, wherein each non-originating snooping master has cache memory, and wherein some, but less than all the cache memories, may have the data requested by an originating snooping master and wherein the needed data in a non-originating snooping master is marked as updated, and wherein a main memory having addresses for all data is connected to the bus macro.Only those non-originating snooping masters which may have the requested data are queried. All the non-originating snooping masters that have been queried reply. If a non-originating snooping master has the requested data marked as updated, that non-originating snooping master returns the updated data to the originating snooping master and possibly to the main memory. If none of the non-originating snooping masters has the requested data marked as updated, then the requested data is read from main memory.

摘要翻译： 一种用于窥探连接到总线宏的多个窥探主机的高速缓冲存储器的方法和结构，其中每个非起始侦听主机具有高速缓冲存储器，并且其中一些但是小于所有高速缓存存储器可以具有由始发侦听器请求的数据 主站，并且其中非起始侦听主控器中的所需数据被标记为更新，并且其中具有用于所有数据的地址的主存储器连接到总线宏。 只有那些可能具有请求的数据的非始发侦听主机才被查询。 所有被查询的非始发侦听主人都回复。 如果非始发侦听主机具有被标记为更新的请求数据，则该非起始侦听主机会将更新的数据返回给始发侦听主机，并将其返回到主内存。 如果非始发侦听主机中没有一个被标记为已更新的请求数据，则从主存储器读取所请求的数据。

公开(公告)号：US5734600A

公开(公告)日：1998-03-31

申请号：US219694

申请日：1994-03-29

申请人： James N. Dieffenderfer ,  James W. Dieffenderfer

发明人： James N. Dieffenderfer ,  James W. Dieffenderfer

IPC分类号： G06F7/52

CPC分类号： G06F7/5334 ,  G06F7/5336 ,  G06F7/5338

摘要： A multiplier efficiently multiplies signed or unsigned binary polynomial operands. The multiplier includes storage means for temporary storage of a current multiplier and a current multiplicand each of which being binary polynomials, one or more Booth decoders for examining multiplier bits iteratively in predetermined groups and presenting a Booth decoder output as one set of inputs to a plurality of delta generators and a partial product delta generator. Another set of inputs to the delta generators and the partial product delta generator is a predetermined group of bits from a multiplicand. The outputs of the partial product delta generator are multiplexed with outputs of the partial product register to provide inputs of an adder array. The adder array has outputs to a parallel adder which generates partial products which are then fed back to the multiplexor. The operation of the multiplier is controlled by a state machine wherein the multiplexor selects one of a plurality of inputs to the multiplexor as output depending upon the state condition of the state machine.

摘要翻译： 乘数有效地乘以带符号或无符号的二进制多项式操作数。 乘法器包括用于临时存储当前乘法器的存储装置和每个都是二进制多项式的当前乘法器，一个或多个布尔解码器，用于在预定组中迭代地检查乘法器位，并将布斯解码器输出作为一组输入提供给多个 的三角洲发电机和部分产品增量发生器。 来自增量发生器和部分乘积增量发生器的另一组输入是来自被乘数的预定比特组。 部分乘积增量发生器的输出与部分乘积寄存器的输出复用，以提供加法器阵列的输入。 加法器阵列具有输出到并行加法器，该并行加法器产生部分积，然后反馈给多路复用器。 乘法器的操作由状态机控制，其中多路复用器根据状态机的状态来选择多路复用器的多个输入中的一个作为输出。