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    Segmented Pipeline Flushing for Mispredicted Branches
    2.
    发明申请
    Segmented Pipeline Flushing for Mispredicted Branches 有权
    分段管道冲洗用于预测分支

    公开(公告)号：US20080177992A1

    公开(公告)日：2008-07-24

    申请号：US11626443

    申请日：2007-01-24

    申请人： Rodney Wayne Smith ,  James Norris Dieffenderfer ,  Michael Scott McIlvaine ,  Thomas Andrew Sartorius

    发明人： Rodney Wayne Smith ,  James Norris Dieffenderfer ,  Michael Scott McIlvaine ,  Thomas Andrew Sartorius

    IPC分类号： G06F9/38

    CPC分类号： G06F9/384 ,  G06F9/3842 ,  G06F9/3863 ,  G06F9/3867

    摘要： A processor pipeline is segmented into an upper portion—prior to instructions going out of program order—and one or more lower portions beyond the upper portion. The upper pipeline is flushed upon detecting that a branch instruction was mispredicted, minimizing the delay in fetching of instructions from the correct branch target address. The lower pipelines may continue execution until the mispredicted branch instruction confirms, at which time all uncommitted instructions are flushed from the lower pipelines. Existing exception pipeline flushing mechanisms may be utilized, by adding a mispredicted branch identifier, reducing the complexity and hardware cost of flushing the lower pipelines.

    摘要翻译： 处理器管线在分配给程序顺序之外的指令之前被分割成上部，并且超出上部的一个或多个下部。 在检测到分支指令被错误预测时，上级流水线被刷新，从而使得从正确的分支目标地址获取指令的延迟最小化。 较低的管道可以继续执行，直到错误预测的分支指令确认，此时所有未提交的指令都从较低管道冲洗。 可以通过添加错误的分支标识符来减少冲洗下层管道的复杂性和硬件成本，来利用现有的异常流水线冲洗机制。

    Power efficient instruction prefetch mechanism
    3.
    发明授权
    Power efficient instruction prefetch mechanism 有权
    高效的指令预取机制

    公开(公告)号：US08661229B2

    公开(公告)日：2014-02-25

    申请号：US12434804

    申请日：2009-05-04

    申请人： Thomas Andrew Sartorius ,  Victor Roberts Augsburg ,  James Norris Dieffenderfer ,  Jeffrey Todd Bridges ,  Michael Scott McIlvaine ,  Rodney Wayne Smith

    发明人： Thomas Andrew Sartorius ,  Victor Roberts Augsburg ,  James Norris Dieffenderfer ,  Jeffrey Todd Bridges ,  Michael Scott McIlvaine ,  Rodney Wayne Smith

    IPC分类号： G06F9/30 ,  G06F9/40 ,  G06F15/00

    CPC分类号： G06F9/3844 ,  G06F9/3804

    摘要： A processor includes a conditional branch instruction prediction mechanism that generates weighted branch prediction values. For weakly weighted predictions, which tend to be less accurate than strongly weighted predictions, the power associating with speculatively filling and subsequently flushing the cache is saved by halting instruction prefetching. Instruction fetching continues when the branch condition is evaluated in the pipeline and the actual next address is known. Alternatively, prefetching may continue out of a cache. To avoid displacing good cache data with instructions prefetched based on a mispredicted branch, prefetching may be halted in response to a weakly weighted prediction in the event of a cache miss.

    摘要翻译： 处理器包括产生加权分支预测值的条件分支指令预测机制。 对于弱加权预测，其倾向于比强加权预测不太准确，通过停止指令预取来节省与推测性填充和随后刷新高速缓存的功率相关联的功率。 当流水线中评估分支条件并且已知实际的下一个地址时，指令获取继续。 或者，可以从高速缓存中继续预取。 为了避免基于错误预测的分支预取的指令移位良好的高速缓存数据，预取可以响应于在高速缓存未命中的情况下的弱加权预测而停止。

    Method and apparatus for managing instruction flushing in a microprocessor's instruction pipeline
    4.
    发明授权
    Method and apparatus for managing instruction flushing in a microprocessor's instruction pipeline 有权
    用于在微处理器指令管线中管理指令冲洗的方法和装置

    公开(公告)号：US07949861B2

    公开(公告)日：2011-05-24

    申请号：US11149773

    申请日：2005-06-10

    申请人： Michael Scott McIlvaine ,  James Norris Dieffenderfer ,  Thomas Andrew Sartorius

    发明人： Michael Scott McIlvaine ,  James Norris Dieffenderfer ,  Thomas Andrew Sartorius

    IPC分类号： G06F7/38 ,  G06F9/00 ,  G06F9/44 ,  G06F15/00

    CPC分类号： G06F9/3861 ,  G06F9/30072 ,  G06F9/3867 ,  G06F12/0855 ,  G06F12/0862 ,  G06F2212/6028

    摘要： In one or more embodiments, a processor includes one or more circuits to flush instructions from an instruction pipeline on a selective basis responsive to detecting a branch misprediction, such that those instructions marked as being dependent on the branch instruction associated with the branch misprediction are flushed. Thus, the one or more circuits may be configured to mark instructions fetched into the processor's instruction pipeline(s) to indicate their branch prediction dependencies, directly or indirectly detect incorrect branch predictions, and directly or indirectly flush instructions in the instruction pipeline(s) that are marked as being dependent on an incorrect branch prediction.

    摘要翻译： 在一个或多个实施例中，处理器包括一个或多个电路，用于响应于检测到分支错误预测而选择性地刷新来自指令流水线的指令，使得标记为依赖于与分支错误预测相关联的分支指令的那些指令被刷新 。 因此，一个或多个电路可以被配置为标记被提取到处理器的指令流水线中以指示其分支预测依赖性的指令，直接或间接地检测不正确的分支预测，以及直接或间接地刷新指令流水线中的指令， 被标记为依赖于不正确的分支预测。

    Segmented pipeline flushing for mispredicted branches
    5.
    发明授权
    Segmented pipeline flushing for mispredicted branches 有权
    分段管道冲洗错误预测的分支

    公开(公告)号：US07624254B2

    公开(公告)日：2009-11-24

    申请号：US11626443

    申请日：2007-01-24

    申请人： Rodney Wayne Smith ,  James Norris Dieffenderfer ,  Michael Scott McIlvaine ,  Thomas Andrew Sartorius

    发明人： Rodney Wayne Smith ,  James Norris Dieffenderfer ,  Michael Scott McIlvaine ,  Thomas Andrew Sartorius

    IPC分类号： G06F9/38

    CPC分类号： G06F9/384 ,  G06F9/3842 ,  G06F9/3863 ,  G06F9/3867

    摘要： A processor pipeline is segmented into an upper portion—prior to instructions going out of program order—and one or more lower portions beyond the upper portion. The upper pipeline is flushed upon detecting that a branch instruction was mispredicted, minimizing the delay in fetching of instructions from the correct branch target address. The lower pipelines may continue execution until the mispredicted branch instruction confirms, at which time all uncommitted instructions are flushed from the lower pipelines. Existing exception pipeline flushing mechanisms may be utilized, by adding a mispredicted branch identifier, reducing the complexity and hardware cost of flushing the lower pipelines.

    摘要翻译： 处理器管线在分配给程序顺序之外的指令之前被分割成上部，并且超出上部的一个或多个下部。 在检测到分支指令被错误预测时，上级流水线被刷新，从而使得从正确的分支目标地址获取指令的延迟最小化。 较低的管道可以继续执行，直到错误预测的分支指令确认，此时所有未提交的指令都从较低管道冲洗。 可以通过添加错误的分支标识符来减少冲洗下层管道的复杂性和硬件成本，来利用现有的异常流水线冲洗机制。

    Power Efficient Instruction Prefetch Mechanism
    6.
    发明申请
    Power Efficient Instruction Prefetch Mechanism 有权
    高效率指令预取机制

    公开(公告)号：US20090210663A1

    公开(公告)日：2009-08-20

    申请号：US12434804

    申请日：2009-05-04

    申请人： Thomas Andrew Sartorius ,  Victor Roberts Augsburg ,  James Norris Dieffenderfer ,  Jeffrey Todd Bridges ,  Michael Scott McIlvaine ,  Rodney Wayne Smith

    发明人： Thomas Andrew Sartorius ,  Victor Roberts Augsburg ,  James Norris Dieffenderfer ,  Jeffrey Todd Bridges ,  Michael Scott McIlvaine ,  Rodney Wayne Smith

    IPC分类号： G06F9/38

    CPC分类号： G06F9/3844 ,  G06F9/3804

    摘要： A processor includes a conditional branch instruction prediction mechanism that generates weighted branch prediction values. For weakly weighted predictions, which tend to be less accurate than strongly weighted predictions, the power associating with speculatively filling and subsequently flushing the cache is saved by halting instruction prefetching. Instruction fetching continues when the branch condition is evaluated in the pipeline and the actual next address is known. Alternatively, prefetching may continue out of a cache. To avoid displacing good cache data with instructions prefetched based on a mispredicted branch, prefetching may be halted in response to a weakly weighted prediction in the event of a cache miss.

    摘要翻译： 处理器包括产生加权分支预测值的条件分支指令预测机制。 对于弱加权预测，其倾向于比强加权预测不太准确，通过停止指令预取来节省与推测性填充和随后刷新高速缓存的功率相关联的功率。 当流水线中评估分支条件并且已知实际的下一个地址时，指令获取继续。 或者，可以从高速缓存中继续预取。 为了避免基于错误预测的分支预取的指令移位良好的高速缓存数据，预取可以响应于在高速缓存未命中的情况下的弱加权预测而停止。

    Qualifying Software Branch-Target Hints with Hardware-Based Predictions
    10.
    发明申请
    Qualifying Software Branch-Target Hints with Hardware-Based Predictions 审中-公开
    合格软件分支 - 基于硬件预测的目标提示

    公开(公告)号：US20140006752A1

    公开(公告)日：2014-01-02

    申请号：US13534649

    申请日：2012-06-27

    申请人： Michael William Morrow ,  James Norris Dieffenderfer ,  Thomas Andrew Sartorius ,  Michael Scott McIlvaine ,  Brian Michael Stempel ,  Daren Eugene Streett

    发明人： Michael William Morrow ,  James Norris Dieffenderfer ,  Thomas Andrew Sartorius ,  Michael Scott McIlvaine ,  Brian Michael Stempel ,  Daren Eugene Streett

    IPC分类号： G06F9/40

    CPC分类号： G06F9/3806 ,  G06F9/322 ,  G06F9/3848

    摘要： A processor architecture to qualify software target-branch hints with hardware-based predictions, the processor including a branch target address cache having entries, where an entry includes a tag field to store an instruction address, a target field to store a target address, and a state field to store a state value. Upon decoding an indirect branch instruction, the processor determines whether an entry in the branch target address cache has an instruction address that matches the address of the decoded indirect branch instruction; and if there is a match, depending upon the state value stored in the entry, the processor will use the stored target address as the predicted target address for the decoded indirect branch instruction, or will use a software provided target address hint if available.

    摘要翻译： 一种处理器架构，用于基于硬件预测来限定软件目标分支提示，所述处理器包括具有条目的分支目标地址高速缓存，其中条目包括用于存储指令地址的标签字段，存储目标地址的目标字段，以及 状态字段来存储状态值。 在解码间接分支指令时，处理器确定分支目标地址高速缓存中的条目是否具有与解码的间接分支指令的地址相匹配的指令地址; 并且如果存在匹配，则根据存储在条目中的状态值，处理器将使用所存储的目标地址作为解码的间接分支指令的预测目标地址，或者将使用提供的软件提供的目标地址提示（如果可用）。