公开(公告)号：US07698536B2

公开(公告)日：2010-04-13

申请号：US11201542

申请日：2005-08-10

申请人： James Norris Dieffenderfer ,  Thomas Andrew Sartorius ,  Jeffrey Todd Bridges ,  Michael Scott McIlvaine ,  Gregory Christopher Burda

发明人： James Norris Dieffenderfer ,  Thomas Andrew Sartorius ,  Jeffrey Todd Bridges ,  Michael Scott McIlvaine ,  Gregory Christopher Burda

IPC分类号： G06F9/00

CPC分类号： G06F9/30105 ,  G06F9/30141

摘要： A register file is disclosed. The register file includes a plurality of registers and a decoder. The decoder may be configured to receive an address for any one of the registers, and disable a read operation to the addressed register if data in the addressed register is invalid.

摘要翻译： 公开了一种寄存器文件。 寄存器文件包括多个寄存器和解码器。 解码器可以被配置为接收任何一个寄存器的地址，并且如果寻址的寄存器中的数据无效，则禁止对寻址的寄存器的读取操作。

公开(公告)号：US20110197021A1

公开(公告)日：2011-08-11

申请号：US12703342

申请日：2010-02-10

申请人： Gregory Christopher Burda ,  Michael Scott McIlvaine ,  Nathan Samuel Nunamaker ,  Yeshwant Nagaraj Kolla

发明人： Gregory Christopher Burda ,  Michael Scott McIlvaine ,  Nathan Samuel Nunamaker ,  Yeshwant Nagaraj Kolla

IPC分类号： G06F12/00

CPC分类号： G06F9/30141 ,  G06F9/3857

摘要： Write-through-read (WTR) comparator circuits and related WTR processes and memory systems are disclosed. The WTR comparator circuits can be configured to perform WTR functions for a multiple port file having one or more read and write ports. One or more WTR comparators in the WTR comparator circuit are configured to compare a read index into a file with a write index corresponding to a write-back stage selected write port among a plurality of write ports that can write data to the entry in the file. The WTR comparators then generate a WTR comparator output indicating whether the write index matches the read index to control a WTR function. In this manner, the WTR comparator circuit can employ less WTR comparators than the number of read and write port combinations. Providing less WTR comparators can reduce power consumption, cost, and area required on a semiconductor die for the WTR comparator circuit.

摘要翻译： 通读（WTR）比较器电路和相关的WTR处理和存储器系统被公开。 WTR比较器电路可以被配置为对具有一个或多个读取和写入端口的多端口文件执行WTR功能。 WTR比较器电路中的一个或多个WTR比较器被配置为将读取的索引与可以将数据写入文件中的条目的多个写入端口中的读取索引与对应于写回阶段选择的写入端口的写入索引进行比较 。 WTR比较器然后产生WTR比较器输出，指示写入索引是否与读取索引匹配以控制WTR功能。 以这种方式，WTR比较器电路可以使用比读取和写入端口组合数更少的WTR比较器。 提供较少的WTR比较器可以降低用于WTR比较器电路的半导体管芯所需的功耗，成本和面积。

公开(公告)号：US08578117B2

公开(公告)日：2013-11-05

申请号：US12703342

申请日：2010-02-10

申请人： Gregory Christopher Burda ,  Michael Scott McIlvaine ,  Nathan Samuel Nunamker ,  Yeshwant Nagaraj Kolla

发明人： Gregory Christopher Burda ,  Michael Scott McIlvaine ,  Nathan Samuel Nunamker ,  Yeshwant Nagaraj Kolla

IPC分类号： G06F12/00

CPC分类号： G06F9/30141 ,  G06F9/3857

摘要： Write-through-read (WTR) comparator circuits and related WTR processes and memory systems are disclosed. The WTR comparator circuits can be configured to perform WTR functions for a multiple port file having one or more read and write ports. One or more WTR comparators in the WTR comparator circuit are configured to compare a read index into a file with a write index corresponding to a write-back stage selected write port among a plurality of write ports that can write data to the entry in the file. The WTR comparators then generate a WTR comparator output indicating whether the write index matches the read index to control a WTR function. In this manner, the WTR comparator circuit can employ less WTR comparators than the number of read and write port combinations. Providing less WTR comparators can reduce power consumption, cost, and area required on a semiconductor die for the WTR comparator circuit.

摘要翻译： 通读（WTR）比较器电路和相关的WTR处理和存储器系统被公开。 WTR比较器电路可以被配置为对具有一个或多个读取和写入端口的多端口文件执行WTR功能。 WTR比较器电路中的一个或多个WTR比较器被配置为将读取的索引与可以将数据写入文件中的条目的多个写入端口中的读取索引与对应于写回阶段选择的写入端口的写入索引进行比较 。 WTR比较器然后产生WTR比较器输出，指示写入索引是否与读取索引匹配以控制WTR功能。 以这种方式，WTR比较器电路可以使用比读取和写入端口组合数更少的WTR比较器。 提供较少的WTR比较器可以降低用于WTR比较器电路的半导体管芯所需的功耗，成本和面积。

公开(公告)号：US06735145B1

公开(公告)日：2004-05-11

申请号：US10065626

申请日：2002-11-04

申请人： Francois Ibrahim Atallah ,  Gregory Christopher Burda ,  Anthony Correale, Jr.

发明人： Francois Ibrahim Atallah ,  Gregory Christopher Burda ,  Anthony Correale, Jr.

IPC分类号： G11C800

CPC分类号： G11C8/08

摘要： A method and circuit for optimizing power consumption and performance of driver circuits are described. More particularly, embodiments of the present invention provide an enhanced driver circuit. The enhanced driver circuit provides a first voltage, and a detector coupled to the enhanced driver that monitors the first voltage. If the first voltage falls below a predetermined value, the enhanced driver increases the first voltage to at least an optimal voltage.

摘要翻译： 描述了用于优化功率消耗和驱动电路性能的方法和电路。 更具体地，本发明的实施例提供增强的驱动器电路。 增强型驱动器电路提供第一电压，以及耦合到增强型驱动器的检测器，其监视第一电压。 如果第一电压下降到预定值以下，则增强型驱动器将第一电压增加至至少最佳电压。

公开(公告)号：US20130185527A1

公开(公告)日：2013-07-18

申请号：US13420779

申请日：2012-03-15

申请人： Joshua L. Puckett ,  Gregory Christopher Burda

发明人： Joshua L. Puckett ,  Gregory Christopher Burda

IPC分类号： G06F12/00

CPC分类号： G06F13/1689 ,  G06F1/3275 ,  G11C7/1048 ,  G11C7/22 ,  G11C8/12 ,  G11C8/18 ,  G11C2207/2272 ,  Y02D10/13 ,  Y02D10/14

摘要： Asymmetrically-arranged memories having reduced current leakage and/or latency, and related systems and methods are disclosed. In one embodiment, a memory comprises a memory access interface (MAI). The memory further comprises a first memory portion(s) accessible by the MAI. The first memory portion(s) has a first latency and a first current leakage. The memory further comprises a second memory portion(s) accessible by the MAI. To provide an asymmetrical memory arrangement, the first latency of the first memory portion(s) is increased such that the second memory portion(s) has a second latency greater than or equal to the first latency and a second current leakage greater than the first current leakage. Accordingly, the overall current leakage of the memory is reduced while not increasing overall latency of the memory. The first and second memory portion(s) may each be comprised of one or more memory sub-bank(s) and/or one or more memory bank(s).

摘要翻译： 公开了具有减小的电流泄漏和/或延迟的非对称排列的存储器以及相关的系统和方法。 在一个实施例中，存储器包括存储器访问接口（MAI）。 存储器还包括可由MAI访问的第一存储器部分。 第一存储器部分具有第一延迟和第一电流泄漏。 存储器还包括可由MAI访问的第二存储器部分。 为了提供不对称的存储器布置，第一存储器部分的第一等待时间增加，使得第二存储器部分具有大于或等于第一等待时间的第二等待时间和大于第一存储器部分的第一等待时间的第二电流泄漏 电流泄漏。 因此，存储器的总体电流泄漏减小，而不增加存储器的总体延迟。 第一和第二存储器部分可以各自包括一个或多个存储器子组和/或一个或多个存储器组。

公开(公告)号：US08315078B2

公开(公告)日：2012-11-20

申请号：US12357767

申请日：2009-01-22

申请人： Gregory Christopher Burda ,  Jason Philip Martzloff ,  Yeshwant Nagaraj Kolla

发明人： Gregory Christopher Burda ,  Jason Philip Martzloff ,  Yeshwant Nagaraj Kolla

IPC分类号： G11C15/00

CPC分类号： G11C15/04 ,  G06F17/30982 ,  Y02D10/45

摘要： Static-based comparators and methods for comparing data are disclosed. The static-based comparator is configured to selectively switch at least one comparator output in response to a comparison of corresponding data with compare data, and a validity indicator for the data. If the validity indicator indicates valid data, the static-based comparator switches to drive the comparator output indicating either a match or mismatch between corresponding compared data. If the validity indicator indicates invalid data, the static-based comparator provides a mismatch on the comparator output without switching the static-based comparator regardless of whether or not the data matches the compare data. In this manner, the static-based comparator does not dissipate power switching the comparator output for data marked invalid. The static-based comparator can be employed in content addressable memories (CAMs) for comparing one or more bits of tag data to corresponding bit(s) of compare data.

摘要翻译： 公开了基于静态的比较器和用于比较数据的方法。 基于静态的比较器被配置为响应于对比数据与比较数据的比较以及数据的有效性指示符来选择性地切换至少一个比较器输出。 如果有效性指示符指示有效数据，则基于静态的比较器切换以驱动比较器输出，指示相应比较数据之间的匹配或不匹配。 如果有效性指示符指示无效数据，则基于静态的比较器会提供比较器输出的不匹配，而不用切换基于静态的比较器，而不管数据是否与比较数据匹配。 以这种方式，基于静态的比较器不会消耗电源切换比较器输出，标记为无效数据。 基于静态的比较器可以用于内容可寻址存储器（CAM）中，用于将标签数据的一个或多个比特与比较数据的相应比特进行比较。

公开(公告)号：US07242624B2

公开(公告)日：2007-07-10

申请号：US11152982

申请日：2005-06-14

申请人： Yeshwant N. Kolla ,  Gregory Christopher Burda ,  Jeffrey Herbert Fischer

发明人： Yeshwant N. Kolla ,  Gregory Christopher Burda ,  Jeffrey Herbert Fischer

IPC分类号： G11C7/00

CPC分类号： G11C7/22 ,  G11C7/18

摘要： Techniques for reducing power when reading a full-swing memory array are disclosed. The full-swing memory array includes a plurality of local bit lines and a global bit line. In order to reduce power consumption, a method of driving the global bit line includes the step of coupling the plurality of local bit lines to the global bit line through a plurality of tri-state devices. The method further includes the steps of generating a global select signal to enable one of the plurality of tri-state devices and selecting a corresponding local bit line to drive the output of the enabled tri-state device. In this way, the global bit line is statically driven so that consecutive reads of bits having the same value read over the global bit line do not result in transitioning the state of the global bit line.

摘要翻译： 公开了在读取全摆幅存储器阵列时降低功率的技术。 全摆幅存储器阵列包括多个局部位线和全局位线。 为了降低功耗，驱动全局位线的方法包括通过多个三态装置将多个局部位线耦合到全局位线的步骤。 该方法还包括以下步骤：产生全局选择信号以使多个三态装置之一能够选择相应的局部位线来驱动所启用的三态装置的输出。 以这种方式，全局位线被静态驱动，使得在全局位线上读取具有相同值的位的连续读取不会导致全局位线的状态的转变。

公开(公告)号：US06320419B1

公开(公告)日：2001-11-20

申请号：US09678971

申请日：2000-10-04

申请人： Gregory Christopher Burda ,  Jeffrey Herbert Fischer ,  Robert Anthony Paniccia

发明人： Gregory Christopher Burda ,  Jeffrey Herbert Fischer ,  Robert Anthony Paniccia

IPC分类号： H03K1900

CPC分类号： G01R31/318594 ,  G01R31/318569 ,  G01R31/318591 ,  G06F7/02

摘要： The present invention provides a method and system for a contention prevention scheme which provides contention prevention during scan-based test without adversely affecting the functional timing of the path circuit. The contention prevention scheme provides a circuit which includes a path circuit gated by a contention prevention circuit (CPC) and the CPC, where the CPC allows functional operation to occur without adversely affecting the functional operation timing, provided that a time skew between two input signals to the CPC is approximately less than a difference between a time delay associated with a scan-based test logic value and a time delay associated with a functional logic value. With a contention prevention circuit tuned in this manner, a static logical value during functional mode is provided, indicating no contention, which avoids adversely affecting the functional timing of the path circuit.

摘要翻译： 本发明提供了一种用于争用预防方案的方法和系统，其在基于扫描的测试期间提供争用预防，而不会不利地影响路径电路的功能定时。 争用预防方案提供一种电路，其包括由竞争防止电路（CPC）和CPC门控的路径电路，其中CPC允许功能操作发生而不会不利地影响功能操作时序，只要两个输入信号之间的时间偏移 到CPC大致小于与基于扫描的测试逻辑值相关联的时间延迟与与功能逻辑值相关联的时间延迟之间的差异。 利用以这种方式调整的争用防御电路，提供了在功能模式期间的静态逻辑值，指示没有争用，这避免了对路径电路的功能定时的不利影响。

公开(公告)号：US20100182816A1

公开(公告)日：2010-07-22

申请号：US12357767

申请日：2009-01-22

申请人： Gregory Christopher Burda ,  Jason Philip Martzloff ,  Yeshwant Nagaraj Kolla

发明人： Gregory Christopher Burda ,  Jason Philip Martzloff ,  Yeshwant Nagaraj Kolla

IPC分类号： G11C15/00

CPC分类号： G11C15/04 ,  G06F17/30982 ,  Y02D10/45

摘要： Static-based comparators and methods for comparing data are disclosed. The static-based comparator is configured to selectively switch at least one comparator output in response to a comparison of corresponding data with compare data, and a validity indicator for the data. If the validity indicator indicates valid data, the static-based comparator switches to drive the comparator output indicating either a match or mismatch between corresponding compared data. If the validity indicator indicates invalid data, the static-based comparator provides a mismatch on the comparator output without switching the static-based comparator regardless of whether or not the data matches the compare data. In this manner, the static-based comparator does not dissipate power switching the comparator output for data marked invalid. The static-based comparator can be employed in content addressable memories (CAMs) for comparing one or more bits of tag data to corresponding bit(s) of compare data.

摘要翻译： 公开了基于静态的比较器和用于比较数据的方法。 基于静态的比较器被配置为响应于对比数据与比较数据的比较以及数据的有效性指示符来选择性地切换至少一个比较器输出。 如果有效性指示符指示有效数据，则基于静态的比较器切换以驱动比较器输出，指示相应比较数据之间的匹配或不匹配。 如果有效性指示符指示无效数据，则基于静态的比较器会提供比较器输出的不匹配，而不用切换基于静态的比较器，而不管数据是否与比较数据匹配。 以这种方式，基于静态的比较器不会消耗电源切换比较器输出，标记为无效数据。 基于静态的比较器可以用于内容可寻址存储器（CAM）中，用于将标签数据的一个或多个比特与比较数据的相应比特进行比较。