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1.发明授权Method and apparatus for multi-stage hang recovery in an out-of-order microprocessor 失效用于在无序微处理器中进行多级挂机恢复的方法和装置公开(公告)号：US06543003B1
公开(公告)日：2003-04-01
申请号：US09436106
申请日：1999-11-08
申请人： Michael Stephen Floyd , James Allan Kahle , Hung Qui Le , Larry Scott Leitner , Kevin Franklin Reick
发明人： Michael Stephen Floyd , James Allan Kahle , Hung Qui Le , Larry Scott Leitner , Kevin Franklin Reick
IPC分类号： G06F1100
CPC分类号： G06F9/3885 , G06F9/3861 , G06F11/0757 , G06F11/1405
摘要： A method and apparatus for recovering from a hang condition in a processor having a plurality of execution units. Monitoring is performed to detect a hang condition. Responsive to detecting a hang condition, instructions dispatched to the plurality of execution units are flushed.
摘要翻译： 一种用于在具有多个执行单元的处理器中从挂起状态恢复的方法和装置。 执行监视以检测挂起状况。 响应于检测挂起状况，分配给多个执行单元的指令被刷新。
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2.发明授权Method and apparatus for patching problematic instructions in a microprocessor using software interrupts 有权使用软件中断在微处理器中修补有问题的指令的方法和装置公开(公告)号：US06631463B1
公开(公告)日：2003-10-07
申请号：US09436103
申请日：1999-11-08
申请人： Michael Stephen Floyd , James Allan Kahle , Hung Qui Le , John Anthony Moore , Kevin Franklin Reick , Edward John Silha
发明人： Michael Stephen Floyd , James Allan Kahle , Hung Qui Le , John Anthony Moore , Kevin Franklin Reick , Edward John Silha
IPC分类号： G06F900
CPC分类号： G06F9/382 , G06F9/3017 , G06F9/3802 , G06F9/3861
摘要： A method and apparatus for patching a problematic instruction within a pipelined processor in a data processing system is presented. A plurality of instructions are fetched, and the plurality of instructions are matched against at least one match condition to generate a matched instruction. The match conditions may include matching the opcode of an instruction, the pre-decode bits of an instruction, a type of instruction, or other conditions. A matched instruction may be marked using a match bit that accompanies the instruction through the instruction pipeline. The matched instruction is then replaced with an internal opcode or internal instruction that causes the instruction scheduling unit to take a special software interrupt. The problematic instruction is then patched through the execution of a set of instructions that cause the desired logical operation of the problematic instruction.
摘要翻译： 提出了一种用于在数据处理系统中的流水线处理器内修补有问题的指令的方法和装置。 获取多个指令，并且将多个指令与至少一个匹配条件进行匹配以生成匹配的指令。 匹配条件可以包括匹配指令的操作码，指令的预解码位，指令的类型或其他条件。 可以使用伴随指令的匹配位通过指令流水线来标记匹配指令。 匹配的指令被替换为内部操作码或内部指令，使指令调度单元进行特殊的软件中断。 然后通过执行导致有问题的指令的期望的逻辑操作的一组指令来修补有问题的指令。
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3.发明授权Method and apparatus for a high-speed serial communications bus protocol with positive acknowledgement 失效具有正确确认的高速串行通信总线协议的方法和装置公开(公告)号：US06529979B1
公开(公告)日：2003-03-04
申请号：US09436105
申请日：1999-11-08
IPC分类号： G06F1314
CPC分类号： G06F13/4217
摘要： A method and apparatus for transferring data using an on-chip bus is presented. A data transaction consisting of an address and data packet is transmitted on an on-chip bus which is a two-wire serial bus consisting of an address line and a data line that connects a plurality of satellites in a daisy-chain fashion to a central source. Each on-chip satellite is associated with a unique identifier. In response to a determination that the transaction is accepted by the satellite, which is determined by the address in the address packet positively comparing to a unique identifier for the satellite, the address packet is modified to provide a positive acknowledgment of a receipt of the address packet back to the central source of the transaction. The address packet is modified by clearing the stop bit of the address packet, i.e. gating off or negating the stop bit. Alternatively, the address packet is otherwise modified to indicate the acceptance of the packet. The source of the address packet will identify that the operation was successful by detecting that the stop bit is cleared from the framed address packet, thereby receiving the positive acknowledgment indication, thus indicating that a successful transaction occurred.
摘要翻译： 提出了使用片上总线传送数据的方法和装置。 由地址和数据分组组成的数据事务在片上总线上发送，片上总线是两线串行总线，由串行方式连接多个卫星的地址线和数据线组成， 资源。 每个片上卫星与唯一标识符相关联。 响应于确定交易被卫星接受，其由地址分组中的地址确定，与卫星的唯一标识符正相比较，地址分组被修改以提供对地址的接收的肯定确认 数据包回到交易的中心来源。 通过清除地址分组的停止位，即关闭或取消停止位来修改地址分组。 或者，地址分组被修改以指示分组的接受。 通过检测到停止位从成帧的地址分组中清除，地址分组的源将识别出操作成功，从而接收到肯定的确认指示，从而指示成功的事务发生。
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4.发明授权Cross-chip communication mechanism in distributed node topology to access free-running scan registers in clock-controlled components 失效分布式节点拓扑中的跨芯片通信机制，用于访问时钟控制组件中的自由运行扫描寄存器公开(公告)号：US07574581B2
公开(公告)日：2009-08-11
申请号：US10425397
申请日：2003-04-28
CPC分类号： G06F15/17337
摘要： A method of communicating between processing units on different integrated circuit chips in a multi-processor computer system by issuing a command from a source processing unit to a destination processing unit, receiving the command at the destination processing unit while the destination processing unit is processing program instructions, and accessing free-running, scan registers in clock-controlled components of the destination processing unit without interrupting processing of the program instructions by the destination processing unit. The access may be a read from status or mode registers of the destination processing unit, or write to control or mode registers. Many processing units can be interconnected in a ring topology, and the access command can be passed from the source processing unit through several other processing units before reaching the destination processing unit.
摘要翻译： 一种在多处理器计算机系统中的不同集成电路芯片上的处理单元之间进行通信的方法，该方法是从源处理单元向目的地处理单元发出命令，在目的地处理单元处理程序时接收命令 指令，以及访问目的地处理单元的时钟控制组件中的自由运行的扫描寄存器，而不中断目的地处理单元对程序指令的处理。 访问可以是从目的地处理单元的状态或模式寄存器读取，或写入控制或模式寄存器。 许多处理单元可以以环形拓扑互连，并且访问命令可以在到达目的地处理单元之前通过其他几个处理单元从源处理单元传递。
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5.发明授权Method and system for performing pseudo-random testing of an integrated circuit 失效用于执行集成电路的伪随机测试的方法和系统公开(公告)号：US06393594B1
公开(公告)日：2002-05-21
申请号：US09372698
申请日：1999-08-11
申请人： Carl J. Anderson , Michael Stephen Floyd , Larry Scott Leitner , Bradley McCredie , Kevin Franklin Reick , Jennifer Lane Vargus
发明人： Carl J. Anderson , Michael Stephen Floyd , Larry Scott Leitner , Bradley McCredie , Kevin Franklin Reick , Jennifer Lane Vargus
IPC分类号： G06F1100
CPC分类号： G01R31/318385 , G01R31/3183
摘要： A method and system for testing an integrated circuit. A test substrate is provided which is manufactured by the same particular production technology for which the integrated circuit is designed. A pattern generator for generating test data and a result checker for comparing output data are embedded on the test substrate. Isolated portions of circuitry of the integrated circuit are selectively embedded onto the test substrate. Test data from the pattern generator is applied to the isolated portions of circuitry under a first operating condition. The data output from the isolated portions of circuitry is selectively recorded into the result checker. The isolated portions of circuitry are then subjected to testing by applying test data from the pattern generator to the isolated portions of circuitry under a second operating condition. Errors in the isolated portions of circuitry are detected with the result checker by comparing data output from the isolated portions of circuitry with the selectively recorded data output, such that the integrated circuit is tested by subsets, independently of testing the integrated circuit in its entirety.
摘要翻译： 一种用于测试集成电路的方法和系统。 提供了通过设计集成电路的相同特定制造技术制造的测试基板。 用于产生测试数据的图形发生器和用于比较输出数据的结果检查器嵌入在测试基板上。 集成电路的电路的隔离部分选择性地嵌入到测试基板上。 来自图案发生器的测试数据被应用于在第一操作条件下的电路的隔离部分。 从电路的隔离部分输出的数据被选择性地记录到结果检查器中。 然后通过在第二操作条件下将来自图案发生器的测试数据应用到电路的隔离部分来对电路的隔离部分进行测试。 通过将来自电路的隔离部分的输出的数据与选择性记录的数据输出进行比较来检测电路的隔离部分中的错误，使得集成电路被子集测试，独立于集成电路的整体测试。
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6.发明授权Method to operate cache-inhibited memory mapped commands to access registers 失效操作缓存禁止的内存映射命令访问寄存器的方法公开(公告)号：US07392350B2
公开(公告)日：2008-06-24
申请号：US11055160
申请日：2005-02-10
申请人： James Stephen Fields, Jr. , Michael Stephen Floyd , Paul Frank Lecocq , Larry Scott Leitner , Kevin Franklin Reick
发明人： James Stephen Fields, Jr. , Michael Stephen Floyd , Paul Frank Lecocq , Larry Scott Leitner , Kevin Franklin Reick
IPC分类号： G06F13/28
CPC分类号： G06F9/3885 , G06F9/30003 , G06F9/30101 , G06F9/30181 , G06F12/0888
摘要： In a multiprocessor environment, by executing cache-inhibited reads or writes to registers, a scan communication is used to rapidly access registers inside and outside a chip originating the command. Cumbersome locking of the memory location may be thus avoided. Setting of busy latches at the outset virtually eliminates the chance of collisions, and status bits are set to inform the requesting core processor that a command is done and free of error, if that is the case.
摘要翻译： 在多处理器环境中，通过对寄存器执行高速缓存禁止读或写操作，使用扫描通信来快速访问发起命令的芯片内外的寄存器。 因此可以避免存储器位置的繁琐的锁定。 一开始就设置忙锁实际上消除了冲突的机会，并且设置状态位以通知请求的核心处理器完成命令并且没有错误，如果是这样的话。
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7.发明授权Dynamic, Non-invasive detection of hot-pluggable problem components and re-active re-allocation of system resources from problem components 有权动态，非侵入式检测热插拔问题组件，并从问题组件重新分配系统资源公开(公告)号：US07117388B2
公开(公告)日：2006-10-03
申请号：US10424278
申请日：2003-04-28
IPC分类号： G06F11/00
CPC分类号： G06F11/2043 , G06F11/2028 , G06F11/2289
摘要： A method, system, and data processing system for dynamic detection of problem components in a hot-plug processing system and automatic removal of the problem component via hot-removal methods without disrupting processing of the overall system. A data processing system that provides a non-disruptive, hot-plug functionality is designed with a additional logic for initiating and/or completing a sequence of factory level tests on hot-pluggable components to determine if the component if functioning properly. When a component is not functioning properly, the OS re-allocates the workload of the component to other component so the system, and when the OS completes the re-allocation, the service element initiates the hot removal of the component so that the component is logically and electrically separated from the system.
摘要翻译： 一种用于动态检测热插拔处理系统中的问题组件的方法，系统和数据处理系统，并且通过热删除方法自动移除问题组件，而不会中断整个系统的处理。 提供无中断的热插拔功能的数据处理系统设计有一个额外的逻辑，用于启动和/或完成热插拔组件上的一系列工厂级测试，以确定组件是否正常工作。 当组件运行不正常时，操作系统将组件的工作负载重新分配给其他组件，以便系统，并且当操作系统完成重新分配时，服务组件启动组件的热删除，以使组件 与系统逻辑和电气分离。
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8.发明授权Non-disruptive, dynamic hot-plug and hot-remove of server nodes in an SMP 有权SMP中服务器节点的无中断，动态热插拔和热删除公开(公告)号：US06990545B2
公开(公告)日：2006-01-24
申请号：US10424277
申请日：2003-04-28
IPC分类号： G06F13/00
CPC分类号： G06F13/4081
摘要： A data processing system that provides hot-plug add and remove functionality for individual, hot-pluggable components without disrupting current operations of the overall processing system. The processing system includes an interconnect fabric that includes hot plug connector at which an external hot-pluggable component can be coupled to the data processing system and logic components include configuration logic and routing and operating logic. When a hot-pluggable component is connected to the hot plug connector, the service element automatically detects the connection and selects the correct configuration file for the extended system. Once the configuration file is loaded and the system checks of the new element indicates the new element is ready for integration, the new element is integrated into the existing system, and the OS allocates workload to the new element. From a customer perspective, the entire process thus occurs without powering down or disrupting the operation of the existing element.
摘要翻译： 一种数据处理系统，可为单个热插拔组件提供热插拔添加和删除功能，而不会中断整个处理系统的当前操作。 处理系统包括互连结构，其包括热插拔连接器，外部可热插拔组件可以连接到数据处理系统，逻辑组件包括配置逻辑和路由和操作逻辑。 当热插拔组件连接到热插拔连接器时，服务元件会自动检测连接并为扩展系统选择正确的配置文件。 一旦加载了配置文件，并且新元素的系统检查指示新元素可以进行集成，则将新元素集成到现有系统中，并且操作系统将工作负载分配给新元素。 从客户的角度来看，整个过程都是在不掉电或破坏现有元素的操作的情况下进行的。
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9.发明授权Early clock fault detection method and circuit for detecting clock faults in a multiprocessing system 有权用于检测多处理系统中的时钟故障的早期时钟故障检测方法和电路公开(公告)号：US07089462B2
公开(公告)日：2006-08-08
申请号：US10418499
申请日：2003-04-17
CPC分类号： G06F11/1604 , G06F11/1608
摘要： An early clock fault detection method and circuit for detecting clock faults in a multiprocessing system provides an error system that can be used to shutdown the multiprocessing system or a processor before errors caused by loss of synchronization between multiple processors can propagate from the processor causing storage or other systems to be corrupted. The detection circuit counts cycles of a high-frequency internal processor clock generated by multiplying an external master clock signal and detects whether or not a predetermined number of clock cycles have elapsed between transitions of the external master clock signal. The detection circuit provides a clock fault output within less than a master clock cycle, which can be used to shut down the processor, system or interconnect between processors, preventing loss or corruption of data before the high-frequency clock can drift enough to cause errors.
摘要翻译： 用于检测多处理系统中的时钟故障的早期时钟故障检测方法和电路提供了可以用于关闭多处理系统或处理器的错误系统，所述错误系统或处理器在由多个处理器之间的同步丢失引起的错误可能从处理器传播导致存储或 其他系统被破坏。 检测电路对通过乘以外部主时钟信号而产生的高频内部处理器时钟的周期进行计数，并且检测在外部主时钟信号的转换之间是否经过了预定数量的时钟周期。 检测电路在小于主时钟周期内提供时钟故障输出，可用于关闭处理器，处理器之间的系统或互连，防止在高频时钟漂移足够导致错误之前丢失或损坏数据 。
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10.发明授权Method and apparatus for harvesting problematic code sections aggravating hardware design flaws in a microprocessor 失效用于收集有问题的代码段的方法和装置加重了微处理器中的硬件设计缺陷公开(公告)号：US06745321B1
公开(公告)日：2004-06-01
申请号：US09436104
申请日：1999-11-08
IPC分类号： G06F1122
CPC分类号： G06F11/0721 , G06F9/3836 , G06F9/3838 , G06F9/3857 , G06F9/3859 , G06F9/3861 , G06F11/079
摘要： A method and apparatus for harvesting problematic code sections that may cause a hang condition based on a hardware design flaw is presented. Monitoring is performed to detect a hang condition. Responsive to detecting a hang condition, steps are employed by hardware and/or software to recover from a hang condition, such as flushing instructions dispatched to the plurality of execution units. Upon successful completion of hang recovery, a debug interrupt is injected, causing a debug interrupt handler to be immediately involved before the resumption of normal execution. The debug interrupt handler may then harvest problematic code sections in the undisturbed execution error that may have caused the hang condition.
摘要翻译： 提出了一种用于收集可能导致基于硬件设计缺陷的挂起状况的有问题的代码段的方法和装置。 执行监视以检测挂起状况。 响应于检测挂起状况，硬件和/或软件采用步骤从挂起状态恢复，诸如分配给多个执行单元的刷新指令。 在成功完成挂起恢复后，将注入调试中断，导致在恢复正常执行之前立即执行调试中断处理程序。 调试中断处理程序可能会收到可能导致挂起状况的未受干扰的执行错误中的有问题的代码段。
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