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    Method and apparatus for a high-speed serial communications bus protocol with positive acknowledgement
    2.
    发明授权
    Method and apparatus for a high-speed serial communications bus protocol with positive acknowledgement 失效
    具有正确确认的高速串行通信总线协议的方法和装置

    公开(公告)号：US06529979B1

    公开(公告)日：2003-03-04

    申请号：US09436105

    申请日：1999-11-08

    申请人： Michael Stephen Floyd ,  Larry Scott Leitner ,  Kevin Franklin Reick

    发明人： Michael Stephen Floyd ,  Larry Scott Leitner ,  Kevin Franklin Reick

    IPC分类号： G06F1314

    CPC分类号： G06F13/4217

    摘要： A method and apparatus for transferring data using an on-chip bus is presented. A data transaction consisting of an address and data packet is transmitted on an on-chip bus which is a two-wire serial bus consisting of an address line and a data line that connects a plurality of satellites in a daisy-chain fashion to a central source. Each on-chip satellite is associated with a unique identifier. In response to a determination that the transaction is accepted by the satellite, which is determined by the address in the address packet positively comparing to a unique identifier for the satellite, the address packet is modified to provide a positive acknowledgment of a receipt of the address packet back to the central source of the transaction. The address packet is modified by clearing the stop bit of the address packet, i.e. gating off or negating the stop bit. Alternatively, the address packet is otherwise modified to indicate the acceptance of the packet. The source of the address packet will identify that the operation was successful by detecting that the stop bit is cleared from the framed address packet, thereby receiving the positive acknowledgment indication, thus indicating that a successful transaction occurred.

    摘要翻译： 提出了使用片上总线传送数据的方法和装置。 由地址和数据分组组成的数据事务在片上总线上发送，片上总线是两线串行总线，由串行方式连接多个卫星的地址线和数据线组成， 资源。 每个片上卫星与唯一标识符相关联。 响应于确定交易被卫星接受，其由地址分组中的地址确定，与卫星的唯一标识符正相比较，地址分组被修改以提供对地址的接收的肯定确认 数据包回到交易的中心来源。 通过清除地址分组的停止位，即关闭或取消停止位来修改地址分组。 或者，地址分组被修改以指示分组的接受。 通过检测到停止位从成帧的地址分组中清除，地址分组的源将识别出操作成功，从而接收到肯定的确认指示，从而指示成功的事务发生。

    Cross-chip communication mechanism in distributed node topology to access free-running scan registers in clock-controlled components
    4.
    发明授权
    Cross-chip communication mechanism in distributed node topology to access free-running scan registers in clock-controlled components 失效
    分布式节点拓扑中的跨芯片通信机制，用于访问时钟控制组件中的自由运行扫描寄存器

    公开(公告)号：US07574581B2

    公开(公告)日：2009-08-11

    申请号：US10425397

    申请日：2003-04-28

    申请人： Michael Stephen Floyd ,  Larry Scott Leitner ,  Kevin Franklin Reick ,  Kevin Dennis Woodling

    发明人： Michael Stephen Floyd ,  Larry Scott Leitner ,  Kevin Franklin Reick ,  Kevin Dennis Woodling

    IPC分类号： G06F15/00 ,  G06F15/76

    CPC分类号： G06F15/17337

    摘要： A method of communicating between processing units on different integrated circuit chips in a multi-processor computer system by issuing a command from a source processing unit to a destination processing unit, receiving the command at the destination processing unit while the destination processing unit is processing program instructions, and accessing free-running, scan registers in clock-controlled components of the destination processing unit without interrupting processing of the program instructions by the destination processing unit. The access may be a read from status or mode registers of the destination processing unit, or write to control or mode registers. Many processing units can be interconnected in a ring topology, and the access command can be passed from the source processing unit through several other processing units before reaching the destination processing unit.

    摘要翻译： 一种在多处理器计算机系统中的不同集成电路芯片上的处理单元之间进行通信的方法，该方法是从源处理单元向目的地处理单元发出命令，在目的地处理单元处理程序时接收命令 指令，以及访问目的地处理单元的时钟控制组件中的自由运行的扫描寄存器，而不中断目的地处理单元对程序指令的处理。 访问可以是从目的地处理单元的状态或模式寄存器读取，或写入控制或模式寄存器。 许多处理单元可以以环形拓扑互连，并且访问命令可以在到达目的地处理单元之前通过其他几个处理单元从源处理单元传递。

    Method and system for performing pseudo-random testing of an integrated circuit
    5.
    发明授权
    Method and system for performing pseudo-random testing of an integrated circuit 失效
    用于执行集成电路的伪随机测试的方法和系统

    公开(公告)号：US06393594B1

    公开(公告)日：2002-05-21

    申请号：US09372698

    申请日：1999-08-11

    申请人： Carl J. Anderson ,  Michael Stephen Floyd ,  Larry Scott Leitner ,  Bradley McCredie ,  Kevin Franklin Reick ,  Jennifer Lane Vargus

    发明人： Carl J. Anderson ,  Michael Stephen Floyd ,  Larry Scott Leitner ,  Bradley McCredie ,  Kevin Franklin Reick ,  Jennifer Lane Vargus

    IPC分类号： G06F1100

    CPC分类号： G01R31/318385 ,  G01R31/3183

    摘要： A method and system for testing an integrated circuit. A test substrate is provided which is manufactured by the same particular production technology for which the integrated circuit is designed. A pattern generator for generating test data and a result checker for comparing output data are embedded on the test substrate. Isolated portions of circuitry of the integrated circuit are selectively embedded onto the test substrate. Test data from the pattern generator is applied to the isolated portions of circuitry under a first operating condition. The data output from the isolated portions of circuitry is selectively recorded into the result checker. The isolated portions of circuitry are then subjected to testing by applying test data from the pattern generator to the isolated portions of circuitry under a second operating condition. Errors in the isolated portions of circuitry are detected with the result checker by comparing data output from the isolated portions of circuitry with the selectively recorded data output, such that the integrated circuit is tested by subsets, independently of testing the integrated circuit in its entirety.

    摘要翻译： 一种用于测试集成电路的方法和系统。 提供了通过设计集成电路的相同特定制造技术制造的测试基板。 用于产生测试数据的图形发生器和用于比较输出数据的结果检查器嵌入在测试基板上。 集成电路的电路的隔离部分选择性地嵌入到测试基板上。 来自图案发生器的测试数据被应用于在第一操作条件下的电路的隔离部分。 从电路的隔离部分输出的数据被选择性地记录到结果检查器中。 然后通过在第二操作条件下将来自图案发生器的测试数据应用到电路的隔离部分来对电路的隔离部分进行测试。 通过将来自电路的隔离部分的输出的数据与选择性记录的数据输出进行比较来检测电路的隔离部分中的错误，使得集成电路被子集测试，独立于集成电路的整体测试。

    INTELLIGENT SMT THREAD HANG DETECT TAKING INTO ACCOUNT SHARED RESOURCE CONTENTION/BLOCKING
    8.
    发明申请
    INTELLIGENT SMT THREAD HANG DETECT TAKING INTO ACCOUNT SHARED RESOURCE CONTENTION/BLOCKING 有权
    智能SMT螺纹连接检测进入帐户共享资源内容/阻塞

    公开(公告)号：US20080141000A1

    公开(公告)日：2008-06-12

    申请号：US12033385

    申请日：2008-02-19

    申请人： Michael Stephen Floyd ,  Larry Scott Leitner

    发明人： Michael Stephen Floyd ,  Larry Scott Leitner

    IPC分类号： G06F9/30

    CPC分类号： G06F9/3851 ,  G06F9/3012 ,  G06F9/30123 ,  G06F9/3013 ,  G06F9/3842 ,  G06F9/3867 ,  G06F11/0715 ,  G06F11/0721 ,  G06F11/0757 ,  G06F11/1407

    摘要： Monitoring is performed to detect a hang condition. A timer is set to detect a hang based on a core hang limit. If a thread hangs for the duration of the core hang limit, then a core hang is detected. If the thread is performing an external memory transaction, then the timer is increased to a longer memory hang limit. If the thread is waiting for a shared resource, then the timer may be increased to the longer memory hang limit if another thread or, more particularly, the thread blocking the resource has a pending memory transaction. Responsive to detecting a hang condition, instructions dispatched to the plurality of execution units may be flushed, or the processor may be reset and restored to a previously known good, checkpointed architected state.

    摘要翻译： 执行监视以检测挂起状况。 一个定时器被设置为基于核心挂起限制来检测挂起。 如果线程在核心挂起限制的持续时间内挂起，则会检测到核心挂起。 如果线程正在执行外部存储器事务，则定时器增加到更长的内存挂起限制。 如果线程正在等待共享资源，则如果另一个线程，更具体地说，阻塞资源的线程具有未决的存储器事务，则定时器可​​能会增加到更长的内存挂起限制。 响应于检测挂起状况，可以刷新发送到多个执行单元的指令，或者可以将处理器复位并恢复到先前已知的良好的，检查点的架构状态。

    Intelligent SMT thread hang detect taking into account shared resource contention/blocking
    9.
    发明授权
    Intelligent SMT thread hang detect taking into account shared resource contention/blocking 有权
    智能SMT线程挂机检测考虑到共享资源争用/阻塞

    公开(公告)号：US07343476B2

    公开(公告)日：2008-03-11

    申请号：US11055044

    申请日：2005-02-10

    申请人： Michael Stephen Floyd ,  Larry Scott Leitner

    发明人： Michael Stephen Floyd ,  Larry Scott Leitner

    IPC分类号： G06F9/30

    CPC分类号： G06F9/3851 ,  G06F9/3012 ,  G06F9/30123 ,  G06F9/3013 ,  G06F9/3842 ,  G06F9/3867 ,  G06F11/0715 ,  G06F11/0721 ,  G06F11/0757 ,  G06F11/1407

    摘要： Monitoring is performed to detect a hang condition. A timer is set to detect a hang based on a core hang limit. If a thread hangs for the duration of the core hang limit, then a core hang is detected. If the thread is performing an external memory transaction, then the timer is increased to a longer memory hang limit. If the thread is waiting for a shared resource, then the timer may be increased to the longer memory hang limit if another thread or, more particularly, the thread blocking the resource has a pending memory transaction. Responsive to detecting a hang condition, instructions dispatched to the plurality of execution units may be flushed, or the processor may be reset and restored to a previously known good, checkpointed architected state.

    摘要翻译： 执行监视以检测挂起状况。 一个定时器被设置为基于核心挂起限制来检测挂起。 如果线程在核心挂起限制的持续时间内挂起，则会检测到核心挂起。 如果线程正在执行外部存储器事务，则定时器增加到更长的内存挂起限制。 如果线程正在等待共享资源，则如果另一个线程，更具体地说，阻塞资源的线程具有未决的存储器事务，则定时器可​​能会增加到更长的内存挂起限制。 响应于检测挂起状况，可以刷新发送到多个执行单元的指令，或者可以将处理器复位并恢复到先前已知的良好的，检查点的架构状态。

    Multi-state logic analyzer integral to a microprocessor
    10.
    发明授权
    Multi-state logic analyzer integral to a microprocessor 失效
    多状态逻辑分析仪与微处理器集成

    公开(公告)号：US06633838B1

    公开(公告)日：2003-10-14

    申请号：US09435071

    申请日：1999-11-04

    申请人： Lakshminarayana Baba Arimilli ,  Michael Stephen Floyd ,  Larry Scott Leitner ,  Kevin F. Reick ,  Jennifer Lane Vargus

    发明人： Lakshminarayana Baba Arimilli ,  Michael Stephen Floyd ,  Larry Scott Leitner ,  Kevin F. Reick ,  Jennifer Lane Vargus

    IPC分类号： G06F1125

    CPC分类号： G06F11/2236

    摘要： The system and method of the present invention is embodied in a multi-state on-chip logic analyzer that is preferably integrated into a VLSI circuit. In general, the logic analyzer is preferably coupled to a multilevel trace array for storing event trace data generated by the logic analyzer. Input and output logic coupled to both the trace array and the logic analyzer allows reading or writing from or to the trace array, and programming of trigger and condition criteria for transitioning states within the logic analyzer. The logic analyzer has the capability match one or more programmable trigger events to satisfy one or more programmable conditions. Further, the logic analyzer preferably has the capability to initialize programmable conditions in desired states, and to store event trace data in an on-chip array for trace data reconstruction and analysis. Trace array input and output logic allows reading or writing from or to the trace array, and programming of trigger and condition criteria for transitioning states within the logic analyzer. Further, the trace array input and output logic is preferably accessible at both the wafer and component stage to allow for testing and debugging of the VLSI circuitry.

    摘要翻译： 本发明的系统和方法体现在优选集成到VLSI电路中的多状态片上逻辑分析仪中。 通常，逻辑分析器优选地耦合到多级跟踪阵列，用于存储由逻辑分析器生成的事件跟踪数据。 耦合到跟踪阵列和逻辑分析仪的输入和输出逻辑器允许从跟踪数组读取或写入数据，以及对逻辑分析器内的转换状态的触发和条件标准进行编程。 逻辑分析仪具有匹配一个或多个可编程触发事件的能力，以满足一个或多个可编程条件。 此外，逻辑分析器优选地具有在期望状态下初始化可编程条件的能力，并且将事件跟踪数据存储在用于跟踪数据重建和分析的片上阵列中。 跟踪数组输入和输出逻辑允许从跟踪数组读取或写入数据，以及对逻辑分析器内的转换状态的触发和条件标准进行编程。 此外，迹线阵列输入和输出逻辑优选在晶片和元件级可访问以允许对VLSI电路进行测试和调试。