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1.发明授权公开(公告)号：US06636523B1
公开(公告)日：2003-10-21
申请号：US09237861
申请日：1999-01-27
IPC分类号： H04L1256
CPC分类号： H04L47/30 , H04L49/205 , H04L49/3027 , H04L49/351 , H04L49/352 , H04L49/90
摘要： A novel method of flow control in a multiport data switching system having a decision making engine for controlling data forwarding between receive ports and at least one transmit port. Data blocks representing received data packets are placed in a plurality of data queues to be processed by the decision making engine. The data queues allocated to the receive ports are monitored to produce a flow control threshold signal for a selected data queue to indicate a heavy traffic condition of a receive port corresponding to the selected data queue. For example, the flow control threshold signal may indicate that the receive port is close to an overflow condition. Monitoring of a selected data queue may be performed by comparing a write pointer indicating a memory location for writing the data blocks into the selected data queue with a read pointer indicating a memory location for reading the data blocks from the selected data queue. The flow control threshold signal is produced when a predetermined number of memory entries in the data queue is occupied.
摘要翻译： 一种具有用于控制接收端口和至少一个发送端口之间的数据转发的决策引擎的多端口数据交换系统中的流控制的新颖方法。 表示接收到的数据分组的数据块被放置在多个数据队列中，由决策引擎处理。 监视分配给接收端口的数据队列，以产生用于选定数据队列的流量控制阈值信号，以指示对应于所选择的数据队列的接收端口的繁重的业务状况。 例如，流量控制阈值信号可以指示接收端口接近溢出状态。 可以通过将指示用于将数据块写入所选择的数据队列的存储器位置的写指针与指示用于从所选择的数据队列读取数据块的存储器位置的读指针进行比较来执行对所选数据队列的监视。 当数据队列中的预定数量的存储器条目被占用时，产生流量控制阈值信号。
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2.发明授权公开(公告)号：US06463032B1
公开(公告)日：2002-10-08
申请号：US09238047
申请日：1999-01-27
IPC分类号： H04L1254
CPC分类号： H04L49/9078 , H04L49/205 , H04L49/3027 , H04L49/351 , H04L49/90 , H04L49/901
摘要： A novel method of overflow data handling in a multiport data switching system having a decision making engine for controlling data forwarding between receive ports and at least one transmit port. Data blocks representing received data packets are placed in data queues corresponding to the receive ports. The data queues are transferred to logic circuitry for processing in accordance with a prescribed algorithm. Then, a forwarding decision is made to determine the transmit port. An overflow bypass is provided to allow at least a portion of a data block to bypass the logic circuitry, when at least one of the data queues is in an overflow state. For example, pointers indicating memory locations for storing the corresponding received data packets may be transferred via the overflow bypass when the overflow state is detected.
摘要翻译： 一种具有用于控制接收端口与至少一个发送端口之间的数据转发的决策引擎的多端口数据交换系统中的溢出数据处理的新颖方法。 表示接收到的数据分组的数据块被放置在对应于接收端口的数据队列中。 数据队列被传送到逻辑电路，以根据规定的算法进行处理。 然后，进行转发决定以确定发送端口。 当至少一个数据队列处于溢出状态时，提供溢出旁路以允许数据块的至少一部分绕过逻辑电路。 例如，当检测到溢出状态时，指示用于存储对应的接收数据分组的存储器位置的指针可以经由溢出旁路传送。
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3.发明授权Arrangement for transmitting data packets from a media access controller across multiple physical links 失效用于从媒体接入控制器跨多个物理链路发送数据分组的装置公开(公告)号：US06330248B1
公开(公告)日：2001-12-11
申请号：US08985719
申请日：1997-12-05
IPC分类号： H04L12413
CPC分类号： H04L25/14
摘要： A gigabit network node having a media access controller outputting data frames at gigabit rates uses multiple 100 MB/s media interface links coupled to a physical interface to enable implementation of a gigabit network using low cost data links. A modified reconciliation layer, also referred to as a media interface, receives a data frame from a gigabit MAC and selectively stores the received packet data into one of a plurality of transmit buffers associated with the respective 100 MB/s media interface links, according to a path selection arbitration logic in the media interface. The path selection arbitration logic may operate according to an equal priority scheme, where each received data frame is routed according to a round-robin scheme. A high priority/low priority scheme may also be used by the path selection arbitration logic, where data frames identified as high priority are temporarily stored in a high priority transmit buffer, and then forwarded to a selected one of the transmit buffers associated with a corresponding 100 MB/s media interface link before outputting data frames from a low priority buffer.
摘要翻译： 具有以千兆比特速率输出数据帧的媒体访问控制器的千兆网络节点使用耦合到物理接口的多个100MB / s媒体接口链路来实现使用低成本数据链路的千兆位网络。 修改后的协调层（也称为媒体接口）从千兆位MAC接收数据帧，并根据相应的100 MB / s媒体接口链路选择性地将接收的分组数据存储到与相应的100 MB / s媒体接口链路相关联的多个传输缓冲器之一中 媒体接口中的路径选择仲裁逻辑。 路径选择仲裁逻辑可以根据相等优先级方案来操作，其中每个接收的数据帧根据循环方案进行路由。 高优先级/低优先级方案也可以由路径选择仲裁逻辑使用，其中标识为高优先级的数据帧被临时存储在高优先级发送缓冲器中，然后转发到与对应的发送缓冲器相关联的所选发送缓冲器 在从低优先级缓冲区输出数据帧之前，需要100 MB / s的媒体接口链接。
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4.发明授权公开(公告)号：US06778547B1
公开(公告)日：2004-08-17
申请号：US09315849
申请日：1999-05-21
申请人： Shashank C. Merchant
发明人： Shashank C. Merchant
IPC分类号： H04L1256
CPC分类号： H04L49/901 , H04L47/50 , H04L49/3009 , H04L49/3027 , H04L49/351 , H04L49/354 , H04L49/90 , H04L49/9047 , H04L49/9073 , H04L49/9078
摘要： An integrated multiport switch operating in a packet switched network utilizes an internal rules checker (IRC) to process data frames. The IRC employs a modular, pipelined architecture that enables data frames to be processed simultaneously, thereby increasing data throughput.
摘要翻译： 在分组交换网络中操作的集成多端口交换机利用内部规则检查器（IRC）来处理数据帧。 IRC采用模块化的流水线架构，可以同时处理数据帧，从而增加数据吞吐量。
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公开(公告)号：US06460088B1
公开(公告)日：2002-10-01
申请号：US09316073
申请日：1999-05-21
申请人： Shashank C. Merchant
发明人： Shashank C. Merchant
IPC分类号： G06F1516
CPC分类号： H04L49/9078 , H04L12/4645 , H04L12/467 , H04L47/50 , H04L47/6215 , H04L49/3027 , H04L49/351 , H04L49/354 , H04L49/90 , H04L49/901
摘要： An integrated multiport switch operating in a packet switched network provides the capability to alter VLAN tags on a port by port basis. An internal rules checker (IRC) employs a modular architecture that enables data frames to be processed simultaneously and increase data throughput. The IRC further generates a port vector, and thereby, outputs a forwarding descriptor that instructs Port Vector FIFO logic (PVF) on how to process the data frame.
摘要翻译： 在分组交换网络中操作的集成多端口交换机提供了逐个端口改变VLAN标签的能力。 内部规则检查器（IRC）采用模块化架构，可以同时处理数据帧并提高数据吞吐量。 IRC还生成端口向量，从而输出指示端口向量FIFO逻辑（PVF）如何处理数据帧的转发描述符。
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6.发明授权Arrangement for determining link latency for maintaining flow control in full-duplex networks 失效确定链路延迟的方案，用于维护全双工网络中的流量控制公开(公告)号：US06222825B1
公开(公告)日：2001-04-24
申请号：US08788821
申请日：1997-01-23
IPC分类号： G01R3108
CPC分类号： H04L12/4625
摘要： Apparatus and method for more precise controlling of congestion on a network, provides for remote controlling of a remote station on the network by a local station to configure the remote station into a remote loopback configuration. With the remote station thus configured, the local station is then able to determine the link latency of the link, during auto-negotiation, for example. Provided with the link latency, a congestion control algorithm in the local station may be adjusted to account for the link latency to better control the input data streams by controlling when the congestion relieving control signal, such as a PAUSE frame, is transmitted to the remote station to inhibit transmission and relieve congestion.
摘要翻译： 用于更精确地控制网络拥塞的设备和方法，提供本地站点对网络上的远程站的远程控制，以将远程站配置成远程环回配置。 因此，如此配置的远程站，例如，在自动协商期间，本地站能够确定链路的链路等待时间。 提供链路延迟时，可以调整本地站中的拥塞控制算法以考虑链路等待时间，以通过控制何时将诸如暂停帧的拥塞消除控制信号发送到远程站点来进行更好地控制输入数据流 车站抑制传播和缓解拥堵。
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7.发明授权Concurrent execution of multiple instructions in cyclic counter based logic component operation stages 失效在循环计数器的逻辑组件操作阶段中并行执行多个指令
公开(公告)号：US6112294A
公开(公告)日：2000-08-29
申请号：US112146
申请日：1998-07-09
CPC分类号： H04L45/742 , G06F9/3867 , H04L49/602 , H04L49/351
摘要： An arrangement in a processor circuit for concurrently executing a plurality of instructions. An instruction control unit concurrently supplies a plurality of instruction addresses to an instruction memory. Each clock cycle, the instruction memory receives one instruction address from the instruction control unit based on a count value and selectively fetches and outputs corresponding to the received instruction address. An instruction decoder decodes, each clock cycle, the instruction output from the instruction memory the preceding clock cycle while identifying a memory address and an instruction operation for each fetched instruction. A memory interface, based on the count value, selectively supplies to an external memory, each clock cycle, one of the supplied memory addresses and identified by the instruction decoder for the respective fetched instructions. A logic unit, based on the count value also, selectively executes, each clock cycle, the instruction operation for the corresponding fetched instruction using memory data retrieved from the supplied memory address. The instruction control unit has program counter circuits that respectively output the instruction addresses. An instruction controller generates program instruction control signals for each of the program counter circuits in response to a corresponding instruction sequence.
摘要翻译： 一种用于并发执行多个指令的处理器电路中的布置。 指令控制单元同时向指令存储器提供多个指令地址。 每个时钟周期，指令存储器基于计数值从指令控制单元接收一个指令地址，并且选择性地取出和输出对应于接收到的指令地址。 指令解码器在每个时钟周期解码从前一个时钟周期的指令存储器输出的指令，同时识别每个获取的指令的存储器地址和指令操作。 存储器接口基于计数值，选择性地向外部存储器提供每个时钟周期，所提供的存储器地址中的一个，并由指令解码器为相应的读取指令标识。 基于计数值的逻辑单元还可以使用从所提供的存储器地址检索的存储器数据选择性地执行每个时钟周期对相应的取出指令的指令操作。 指令控制单元具有分别输出指令地址的程序计数器电路。 指令控制器响应于相应的指令序列产生每个程序计数器电路的程序指令控制信号。
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公开(公告)号：US5995488A
公开(公告)日：1999-11-30
申请号：US766565
申请日：1996-12-13
IPC分类号： H04L12/403 , H04L12/413 , H04L12/56 , G01F11/00
CPC分类号： H04L12/4013 , H04L12/24 , H04L41/00 , H04L47/263 , H04L47/283 , H04L12/403
摘要： Interpacket delay times are modified in full-duplex Ethernet network devices by calculating for each network station a delay interval based on a time to transmit a data packet at the network rate and a calculated time to transmit the data packet at a desired transmission rate. The network station waits the calculated delay time following a packet transmission before transmitting the next data packet, ensuring that the overall output transmission rate of the network station corresponds to the assigned desired transmission rate. The desired transmission rate is received as a media access control (MAC) control frame from a network management entity, such as a switched hub. Hence, each network station operates at the desired transmission rate, minimizing the occurrence of congestion and eliminating the necessity of PAUSE frames.
摘要翻译： 在全双工以太网设备中，通过基于以网络速率发送数据分组的时间和计算出的时间以期望的传输速率传输数据分组来计算每个网络站的延迟时间间隔，在全双工以太网设备中修改分组间延迟时间。 网络站在发送下一个数据包之前等待分组传输后的计算的延迟时间，确保网络站的总输出传输速率对应于所分配的所需传输速率。 从诸如交换式集线器的网络管理实体接收期望的传输速率作为媒体访问控制（MAC）控制帧。 因此，每个网络站以期望的传输速率操作，使拥塞的发生最小化并且消除了暂停帧的必要性。
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9.发明授权Arrangement for transmitting high speed packet data from a media access controller across multiple physical links 失效用于从媒体接入控制器跨多个物理链路发送高速分组数据的装置
公开(公告)号：US6094439A
公开(公告)日：2000-07-25
申请号：US912235
申请日：1997-08-15
IPC分类号： H04L12/413 , H04L29/06 , H04L29/08
CPC分类号： H04L29/06 , H04L69/14 , H04L69/324
摘要： A Gigabit network node having a media access controller outputting packet data at Gigabit rates uses multiple 100 MB/s physical layer links coupled to a physical interface having a data router to enable implementation of a Gigabit network using low cost data links. A modified reconciliation layer, also referred to as a multi-Media Independent Interface (m-MII) selectively transmits at least a portion of the packet data from the MAC onto the plurality of physical layer links. The physical m-MII interface may output separate packet data on separate physical layer links to increase the effective data transmission rate, may output the same packet data on multiple transmission paths to improve quality of service by establishing redundant data links, or any combination thereof. Priority channels may also be provided on selected physical layer links to provide quality of service and cost of service options within an Ethernet work group environment.
摘要翻译： 具有以千兆比特速率输出分组数据的媒体访问控制器的千兆网络节点使用耦合到具有数据路由器的物理接口的多个100MB / s的物理层链路来实现使用低成本数据链路的千兆位网络的实现。 也称为多媒体独立接口（m-MII）的经修改的协调层选择性地将来自MAC的分组数据的至少一部分传输到多个物理层链路上。 物理m-MII接口可以在单独的物理层链路上输出单独的分组数据，以提高有效数据传输速率，可以在多个传输路径上输出相同的分组数据，以通过建立冗余数据链路或其任何组合来提高服务质量。 还可以在所选择的物理层链路上提供优先级信道，以在以太网工作组环境中提供服务质量和服务成本。
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10.发明授权Arrangement for transmitting packet data segments from a media access controller across multiple physical links 失效用于从媒体访问控制器跨多个物理链路发送分组数据段的布置
公开(公告)号：US06081523A
公开(公告)日：2000-06-27
申请号：US985718
申请日：1997-12-05
CPC分类号： H04L47/10 , H04L25/14 , H04L45/245 , H04L47/125 , Y02B60/33
摘要： A Gigabit network node having a media access controller outputting packet data at Gigabit rates uses multiple 100 MB/s media interface links coupled to a physical interface to enable implementation of a Gigabit network using low cost data links. A modified reconciliation layer, also referred to as a media interface, receives a data packet from a Gigabit MAC and divides the received data packet into multiple data segments having a prescribed length. The multiple segments are output on the multiple media interface links according to a prescribed output protocol, enabling a corresponding media interface at the destination station to recompile the data packet from the received segments from the multiple transmission paths. The transmission of the segments upon multiple transmission paths provides an efficient load balancing of data traffic among the multiple transmission paths.
摘要翻译： 具有以千兆比特速率输出分组数据的媒体接入控制器的千兆网络节点使用耦合到物理接口的多个100MB / s媒体接口链路来实现使用低成本数据链路的千兆位网络的实现。 经修改的协调层（也称为媒体接口）从千兆位MAC接收数据包，并将接收到的数据包划分成具有规定长度的多个数据段。 多个段根据规定的输出协议在多个媒体接口链路上输出，使得目的地站处的相应媒体接口可以从多个传输路径中重新编译来自接收到的段的数据分组。 多个传输路径上的段传输提供了多个传输路径之间的数据业务的有效负载平衡。
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