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    Concurrent execution of multiple instructions in cyclic counter based logic component operation stages
    1.
    发明授权
    Concurrent execution of multiple instructions in cyclic counter based logic component operation stages 失效
    在循环计数器的逻辑组件操作阶段中并行执行多个指令

    公开(公告)号：US6112294A

    公开(公告)日：2000-08-29

    申请号：US112146

    申请日：1998-07-09

    Applicant: Shashank C. Merchant ,  Thomas Jefferson Runaldue

    Inventor： Shashank C. Merchant ,  Thomas Jefferson Runaldue

    IPC: G06F9/38 ,  H04L12/56

    CPC classification number: H04L45/742 ,  G06F9/3867 ,  H04L49/602 ,  H04L49/351

    Abstract: An arrangement in a processor circuit for concurrently executing a plurality of instructions. An instruction control unit concurrently supplies a plurality of instruction addresses to an instruction memory. Each clock cycle, the instruction memory receives one instruction address from the instruction control unit based on a count value and selectively fetches and outputs corresponding to the received instruction address. An instruction decoder decodes, each clock cycle, the instruction output from the instruction memory the preceding clock cycle while identifying a memory address and an instruction operation for each fetched instruction. A memory interface, based on the count value, selectively supplies to an external memory, each clock cycle, one of the supplied memory addresses and identified by the instruction decoder for the respective fetched instructions. A logic unit, based on the count value also, selectively executes, each clock cycle, the instruction operation for the corresponding fetched instruction using memory data retrieved from the supplied memory address. The instruction control unit has program counter circuits that respectively output the instruction addresses. An instruction controller generates program instruction control signals for each of the program counter circuits in response to a corresponding instruction sequence.

    Abstract translation: 一种用于并发执行多个指令的处理器电路中的布置。 指令控制单元同时向指令存储器提供多个指令地址。 每个时钟周期，指令存储器基于计数值从指令控制单元接收一个指令地址，并且选择性地取出和输出对应于接收到的指令地址。 指令解码器在每个时钟周期解码从前一个时钟周期的指令存储器输出的指令，同时识别每个获取的指令的存储器地址和指令操作。 存储器接口基于计数值，选择性地向外部存储器提供每个时钟周期，所提供的存储器地址中的一个，并由指令解码器为相应的读取指令标识。 基于计数值的逻辑单元还可以使用从所提供的存储器地址检索的存储器数据选择性地执行每个时钟周期对相应的取出指令的指令操作。 指令控制单元具有分别输出指令地址的程序计数器电路。 指令控制器响应于相应的指令序列产生每个程序计数器电路的程序指令控制信号。

    Contention resolution system in ATM switch
    3.
    发明授权
    Contention resolution system in ATM switch 失效
    ATM交换机中的争用解决系统

    公开(公告)号：US5784374A

    公开(公告)日：1998-07-21

    申请号：US597309

    申请日：1996-02-06

    Applicant: Thomas Jefferson Runaldue

    Inventor： Thomas Jefferson Runaldue

    IPC: H04L12/56 ,  H04Q11/04 ,  H04J3/02

    CPC classification number: H04L12/5601 ,  H04L49/1553 ,  H04L49/1561 ,  H04L49/255 ,  H04Q11/0478 ,  H04L2012/5627 ,  H04L2012/5651 ,  H04L2012/5679

    Abstract: An ATM switch is provided with two stages of crossbar switches with internal blocking paths between the stages. To define priorities of input ports, switches of stage 1 calculate the effective serial numbers of the input ports based on their physical serial numbers and global offset values. To provide dynamic modification of the input port priorities, the global offset values can be changed in each cell cycle of the ATM switch. A sequence of encoded requests for access to required output ports are sent from each switch of stage 1 to each switch of stage 2. Contention arbitration logic in each switch of stage 2 determines which requests may be granted so as to avoid blocking paths between stages 1 and 2, and to prevent out-of-order cell delivery. Signals that acknowledge acceptance of cells and provide information required to establish the serial numbers of the accepted input ports are sent back from each switch of stage 2 to each switch of stage 1. Based on these signals, the cells that will be accepted are routed through the switches of stages 1 and 2 to required output ports. The rejected cells may be queued for transmitting in the next cell cycle.

    Abstract translation: ATM交换机具有两级交叉开关，其中两级之间具有内部阻塞路径。 为了确定输入端口的优先级，阶段1的开关根据其物理序列号和全局偏移量计算输入端口的有效序列号。 为了提供对输入端口优先级的动态修改，可以在ATM交换机的每个单元周期中改变全局偏移值。 从阶段1的每个交换机向阶段2的每个交换机发送用于访问所需输出端口的编码请求序列。阶段2的每个交换机中的争用仲裁逻辑确定可以授予哪些请求，以避免在阶段1之间阻塞路径 和2，并且防止无序细胞递送。 确认接收单元并提供建立接受的输入端口的序列号所需的信息的信号从阶段2的每个开关发送回到阶段1的每个开关。基于这些信号，被接收的单元被路由通过 阶段1和2的开关到所需的输出端口。 被拒绝的小区可以排队等待在下一个小区周期中进行传输。

    Digital phase lock loop and system for digital clock recovery
    5.
    发明授权
    Digital phase lock loop and system for digital clock recovery 失效
    数字锁相环和数字时钟恢复系统

    公开(公告)号：US5812619A

    公开(公告)日：1998-09-22

    申请号：US608165

    申请日：1996-02-28

    Applicant: Thomas Jefferson Runaldue

    Inventor： Thomas Jefferson Runaldue

    IPC: H03L7/06 ,  H03L7/08 ,  H03L7/089 ,  H03L7/099 ,  H04L7/033 ,  H03D3/24 ,  H04L7/02

    CPC classification number: H04L7/0331 ,  H03L7/089 ,  H03L2207/50 ,  H03L7/0991 ,  H04L7/10

    Abstract: A digital phase lock loop and system for data extraction and clock recovery of Ethernet data reduces power consumption, area, and noise sensitivity. In one aspect, a digital phase lock loop (PLL) includes a data extraction and end of transmission delimiter (ETD) circuit, an edge detection comparator coupled to the data extraction and ETD circuit, an up/down counter coupled to the edge detection comparator, and a phase adjustment oscillator coupled to the counter and to the data extraction and ETD circuit for producing phase adjustments in a reference clock signal in accordance with shifts in the frequency of the data. In a system aspect of the present invention, the system receives the data in a digital PLL circuit, and adjusts a phase of a reference clock and a sample clock to track transitions in the data through the digital PLL.

    Abstract translation: 数字锁相环和数据采集系统，以太网数据的数据提取和时钟恢复可以降低功耗，面积和噪声灵敏度。 在一个方面，数字锁相环（PLL）包括数据提取和传输定界符（ETD）结束，耦合到数据提取和ETD电路的边缘检测比较器，耦合到边缘检测比较器的上/下计数器 以及耦合到计数器和数据提取和ETD电路的相位调节振荡器，用于根据数据频率的偏移在参考时钟信号中产生相位调整。 在本发明的系统方面，系统在数字PLL电路中接收数据，并调整参考时钟和采样时钟的相位，以通过数字PLL跟踪数据中的转换。

    Method of and system for pre-fetching input cells in ATM switch
    8.
    发明授权
    Method of and system for pre-fetching input cells in ATM switch 失效
    ATM交换机中预取输入单元的方法和系统

    公开(公告)号：US5687324A

    公开(公告)日：1997-11-11

    申请号：US555021

    申请日：1995-11-08

    Applicant: Patrick Green ,  Thomas Jefferson Runaldue ,  Ronald Bianchini, Jr.

    Inventor： Patrick Green ,  Thomas Jefferson Runaldue ,  Ronald Bianchini, Jr.

    IPC: H04L12/56 ,  G06F13/00

    CPC classification number: H04L12/5601 ,  H04L49/106 ,  H04L49/1553 ,  H04L49/1561 ,  H04L49/203 ,  H04L2012/5651 ,  H04L2012/5681

    Abstract: An ATM switch with multicast capability uses a feedback mechanism for resolving contentions. A multicast network reads N cells from an input queue, replicates multicast cells and translates their addresses in accordance with an external look-up table. The processed N cells are stored in a temporary buffer until information regarding the number (F) of cells fed back due to contention in the previous switching cycle is available. A rotator positions N-F cells from the temporary buffer on inputs of an output network so as to assign the cells from the temporary buffer a lower priority than a priority of the feed back cells. The output network selects the cells that can be switched to their destinations and transfers them to output ports. The cells that cannot be switched due to contention are fed back to be presented for the output network consideration in the next switching cycle. At the same time, a pointer of the input queue is decremented by a factor depending on the number of feedback cells, and the number of multicast and unicast cells in the current switching cycle.

    Abstract translation: 具有组播功能的ATM交换机使用反馈机制来解决争用。 组播网络从输入队列中读取N个单元，根据外部查找表复制多播单元并翻译其地址。 处理的N个单元被存储在临时缓冲器中，直到有关由于在前一个切换周期中的争用而被反馈的单元的数量（F）的信息可用。 旋转器将来自临时缓冲器的N-F个单元从输出网络的输入端定位，从而将来自临时缓冲器的单元分配给比反馈单元优先级低的优先级。 输出网络选择可以切换到目的地的单元，并将其传输到输出端口。 反馈由于竞争而不能切换的单元被反馈以在下一个切换周期中呈现用于输出网络的考虑。 同时，输入队列的指针根据反馈单元的数量以及当前切换周期中的组播和单播小区的数量而减少。

    Clock generation with continuous phase
    9.
    发明授权
    Clock generation with continuous phase 有权
    具有连续相位的时钟发生

    公开(公告)号：US07046064B1

    公开(公告)日：2006-05-16

    申请号：US10817582

    申请日：2004-04-02

    Applicant: Thomas Jefferson Runaldue

    Inventor： Thomas Jefferson Runaldue

    IPC: H03H11/16

    CPC classification number: H03L7/06 ,  H03L7/0814

    Abstract: A clock generation system includes an oscillator and one or more clock generators. The oscillator provides inphase and quadrature oscillator signals having a fixed frequency. Each clock generator receives the oscillator signals and generates a respective output clock signal. Within each clock generator, two weight generators receive two sequences of phase values and generate weights for two analog signals. Two signal generators multiply the inphase and quadrature oscillator signals with the weights from the two weight generators and provide the two analog signals having leading edges determined by the two sequences of phase values. A digital clock generator generates a DCLK signal based on the two analog signals. A divider divides the DCLK signal by N in frequency and provides the output clock signal. A phase generator generates the two sequences of phase values for the two analog signals based on a frequency control value and a phase offset value.

    Abstract translation: 时钟发生系统包括振荡器和一个或多个时钟发生器。 振荡器提供具有固定频率的同相和正交振荡器信号。 每个时钟发生器接收振荡器信号并产生相应的输出时钟信号。 在每个时钟发生器内，两个重量发生器接收两个相位值序列，并产生两个模拟信号的权重。 两个信号发生器将同相和正交振荡器信号与来自两个权重发生器的权重相乘，并提供具有由两个相位值序列确定的前沿的两个模拟信号。 数字时钟发生器基于两个模拟信号产生DCLK信号。 分频器将DCLK信号分频除以N，并提供输出时钟信号。 相位发生器基于频率控制值和相位偏移值生成两个模拟信号的两个相位值序列。

    Reducing the pin count within a switching element through the use of a multiplexer
    10.
    发明授权
    Reducing the pin count within a switching element through the use of a multiplexer 失效
    通过使用多路复用器来减少开关元件内的引脚数

    公开(公告)号：US6108726A

    公开(公告)日：2000-08-22

    申请号：US713489

    申请日：1996-09-13

    Applicant: Thomas Jefferson Runaldue ,  Jayant Kadambi

    Inventor： Thomas Jefferson Runaldue ,  Jayant Kadambi

    IPC: H04L12/56 ,  G06F13/00 ,  H04J3/02

    CPC classification number: H04L49/351

    Abstract: The present invention comprises a system and method for reducing the pin count between a plurality of MAC and PHY devices within a switching element. In this embodiment, the switching element includes a plurality of general serial interfaces for providing connections between respective MAC and PHY devices and each of the plurality of general serial interfaces operates at a first data rate. The system and method comprises a multiplexer coupled to the plurality of general serial interfaces and a pad member including a plurality of pins. The pad member is coupled to the multiplexer and receives multiplexed signals from the plurality of general serial interfaces. The multiplexer operates at a second data rate that is a multiple of the first data rate. Generally, a system and method in accordance with the present invention allows for the multiplexing of a general purpose serial interface (GPSI) to reduce the pin count in some cases by as much as 75% and also synchronize the MAC/PHY interface. In this example, the multiplexer interface uses a total of 7 pins and supports a total of four MAC/PHY connections. If only GPSIs were utilized, 28 pins would be required for this function. The same multiplexing technique will also reduce the MAC/PHY interface in four 100 Mbps connections from 56 pins for a four port system to 18 pins. In each example the multiplexer interface will operate at four times the speed of the general serial interface.

    Abstract translation: 本发明包括一种用于减少开关元件内的多个MAC和PHY器件之间的引脚数的系统和方法。 在该实施例中，开关元件包括多个通用串行接口，用于提供相应MAC和PHY设备之间的连接，并且多个通用串行接口中的每一个以第一数据速率工作。 该系统和方法包括耦合到多个通用串行接口的多路复用器和包括多个引脚的焊盘构件。 焊盘构件耦合到多路复用器并且从多个通用串行接口接收复用的信号。 多路复用器以第一数据速率的倍数的第二数据速率操作。 通常，根据本发明的系统和方法允许多路复用通用串行接口（GPSI），以在一些情况下减少引脚数量高达75％，并且还使MAC / PHY接口同步。 在此示例中，多路复用器接口使用总共7个引脚，并且总共支持四个MAC / PHY连接。 如果仅使用GPSI，则此功能将需要28个引脚。 相同的复用技术还将减少四个100 Mbps连接中的MAC / PHY接口，从56个引脚到四个端口系统到18个引脚。 在每个示例中，多路复用器接口将以通用串行接口的四倍速度运行。

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