公开(公告)号：US20110021019A1

公开(公告)日：2011-01-27

申请号：US12897696

申请日：2010-10-04

申请人： Michael W. Konevecki ,  Usha Raghuram ,  Maitreyee Mahajani ,  Sucheta Nallamothu ,  Andrew J. Walker ,  Tanmay Kumar

发明人： Michael W. Konevecki ,  Usha Raghuram ,  Maitreyee Mahajani ,  Sucheta Nallamothu ,  Andrew J. Walker ,  Tanmay Kumar

IPC分类号： H01L21/768

CPC分类号： H01L27/12 ,  H01L21/28282 ,  H01L21/84 ,  H01L23/535 ,  H01L27/0688 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11551 ,  H01L27/11568 ,  H01L27/11578 ,  H01L29/792 ,  H01L2924/0002 ,  H01L2924/00

摘要： The invention provides for polysilicon vias connecting conductive polysilicon layers formed at different heights. Polysilicon vias are advantageously used in a monolithic three dimensional memory array of charge storage transistors. Polysilicon vias according to the present invention can be used, for example, to connect the channel layer of a first device level of charge storage transistor memory cells to the channel layer of a second device layer of such cells formed above the first device level. Similarly, vias according to the present invention can be used to connect the wordline of a first device level of charge storage transistor memory cells to the channel layer of a second device layer of such cells.

摘要翻译： 本发明提供了连接在不同高度形成的导电多晶硅层的多晶硅通孔。 多晶硅通孔有利地用于电荷存储晶体管的单片三维存储器阵列中。 根据本发明的多晶硅通孔可以用于例如将电荷存储晶体管存储单元的第一器件电平的沟道层连接到形成在第一器件电平之上的这样的单元的第二器件层的沟道层。 类似地，根据本发明的通孔可用于将电荷存储晶体管存储单元的第一器件电平的字线连接到这种单元的第二器件层的沟道层。

公开(公告)号：US20090258462A1

公开(公告)日：2009-10-15

申请号：US12489214

申请日：2009-06-22

申请人： Michael W. Konevecki ,  Usha Raghuram ,  Maitreyee Mahajani ,  Sucheta Nallamothu ,  Andrew J. Walker ,  Tanmay Kumar

发明人： Michael W. Konevecki ,  Usha Raghuram ,  Maitreyee Mahajani ,  Sucheta Nallamothu ,  Andrew J. Walker ,  Tanmay Kumar

IPC分类号： H01L21/82

CPC分类号： H01L27/12 ,  H01L21/28282 ,  H01L21/84 ,  H01L23/535 ,  H01L27/0688 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11551 ,  H01L27/11568 ,  H01L27/11578 ,  H01L29/792 ,  H01L2924/0002 ,  H01L2924/00

摘要： The invention provides for polysilicon vias connecting conductive polysilicon layers formed at different heights. Polysilicon vias are advantageously used in a monolithic three dimensional memory array of charge storage transistors. Polysilicon vias according to the present invention can be used, for example, to connect the channel layer of a first device level of charge storage transistor memory cells to the channel layer of a second device layer of such cells formed above the first device level. Similarly, vias according to the present invention can be used to connect the wordline of a first device level of charge storage transistor memory cells to the channel layer of a second device layer of such cells.

摘要翻译： 本发明提供了连接在不同高度形成的导电多晶硅层的多晶硅通孔。 多晶硅通孔有利地用于电荷存储晶体管的单片三维存储器阵列中。 根据本发明的多晶硅通孔可以用于例如将电荷存储晶体管存储单元的第一器件电平的沟道层连接到形成在第一器件电平之上的这样的单元的第二器件层的沟道层。 类似地，根据本发明的通孔可用于将电荷存储晶体管存储单元的第一器件电平的字线连接到这种单元的第二器件层的沟道层。

公开(公告)号：US07915164B2

公开(公告)日：2011-03-29

申请号：US12897696

申请日：2010-10-04

申请人： Michael W. Konevecki ,  Usha Raghuram ,  Maitreyee Mahajani ,  Sucheta Nallamothu ,  Andrew J. Walker ,  Tanmay Kumar

发明人： Michael W. Konevecki ,  Usha Raghuram ,  Maitreyee Mahajani ,  Sucheta Nallamothu ,  Andrew J. Walker ,  Tanmay Kumar

IPC分类号： H01L21/8246 ,  H01L21/768

CPC分类号： H01L27/12 ,  H01L21/28282 ,  H01L21/84 ,  H01L23/535 ,  H01L27/0688 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11551 ,  H01L27/11568 ,  H01L27/11578 ,  H01L29/792 ,  H01L2924/0002 ,  H01L2924/00

摘要： The invention provides for polysilicon vias connecting conductive polysilicon layers formed at different heights. Polysilicon vias are advantageously used in a monolithic three dimensional memory array of charge storage transistors. Polysilicon vias according to the present invention can be used, for example, to connect the channel layer of a first device level of charge storage transistor memory cells to the channel layer of a second device layer of such cells formed above the first device level. Similarly, vias according to the present invention can be used to connect the wordline of a first device level of charge storage transistor memory cells to the channel layer of a second device layer of such cells.

公开(公告)号：US07915163B2

公开(公告)日：2011-03-29

申请号：US12489214

申请日：2009-06-22

申请人： Michael W. Konevecki ,  Usha Raghuram ,  Maitreyee Mahajani ,  Sucheta Nallamothu ,  Andrew J. Walker ,  Tanmay Kumar

发明人： Michael W. Konevecki ,  Usha Raghuram ,  Maitreyee Mahajani ,  Sucheta Nallamothu ,  Andrew J. Walker ,  Tanmay Kumar

IPC分类号： H01L21/8246 ,  H01L21/768

CPC分类号： H01L27/12 ,  H01L21/28282 ,  H01L21/84 ,  H01L23/535 ,  H01L27/0688 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11551 ,  H01L27/11568 ,  H01L27/11578 ,  H01L29/792 ,  H01L2924/0002 ,  H01L2924/00

摘要： The invention provides for polysilicon vias connecting conductive polysilicon layers formed at different heights. Polysilicon vias are advantageously used in a monolithic three dimensional memory array of charge storage transistors. Polysilicon vias according to the present invention can be used, for example, to connect the channel layer of a first device level of charge storage transistor memory cells to the channel layer of a second device layer of such cells formed above the first device level. Similarly, vias according to the present invention can be used to connect the wordline of a first device level of charge storage transistor memory cells to the channel layer of a second device layer of such cells.

摘要翻译： 本发明提供了连接在不同高度形成的导电多晶硅层的多晶硅通孔。 多晶硅通孔有利地用于电荷存储晶体管的单片三维存储器阵列中。 根据本发明的多晶硅通孔可以用于例如将电荷存储晶体管存储单元的第一器件电平的沟道层连接到形成在第一器件电平之上的这样的单元的第二器件层的沟道层。 类似地，根据本发明的通孔可用于将电荷存储晶体管存储单元的第一器件电平的字线连接到这种单元的第二器件层的沟道层。

公开(公告)号：US07566974B2

公开(公告)日：2009-07-28

申请号：US10955710

申请日：2004-09-29

申请人： Michael W. Konevecki ,  Usha Raghuram ,  Maitreyee Mahajani ,  Tanmay Kumar ,  Sucheta Nallamothu ,  Andrew J. Walker

发明人： Michael W. Konevecki ,  Usha Raghuram ,  Maitreyee Mahajani ,  Tanmay Kumar ,  Sucheta Nallamothu ,  Andrew J. Walker

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/43

CPC分类号： H01L27/12 ,  H01L21/28282 ,  H01L21/84 ,  H01L23/535 ,  H01L27/0688 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11551 ,  H01L27/11568 ,  H01L27/11578 ,  H01L29/792 ,  H01L2924/0002 ,  H01L2924/00

摘要： The invention provides for polysilicon vias connecting conductive polysilicon layers formed at different heights. Polysilicon vias are advantageously used in a monolithic three dimensional memory array of charge storage transistors. Polysilicon vias according to the present invention can be used, for example, to connect the channel layer of a first device level of charge storage transistor memory cells to the channel layer of a second device layer of such cells formed above the first device level. Similarly, vias according to the present invention can be used to connect the wordline of a first device level of charge storage transistor memory cells to the channel layer of a second device layer of such cells.

摘要翻译： 本发明提供了连接在不同高度形成的导电多晶硅层的多晶硅通孔。 多晶硅通孔有利地用于电荷存储晶体管的单片三维存储器阵列中。 根据本发明的多晶硅通孔可以用于例如将电荷存储晶体管存储单元的第一器件电平的沟道层连接到形成在第一器件电平之上的这样的单元的第二器件层的沟道层。 类似地，根据本发明的通孔可用于将电荷存储晶体管存储单元的第一器件电平的字线连接到这种单元的第二器件层的沟道层。

公开(公告)号：US20060071074A1

公开(公告)日：2006-04-06

申请号：US10955710

申请日：2004-09-29

申请人： Michael Konevecki ,  Usha Raghuram ,  Maitreyee Mahajani ,  Sucheta Nallamothu ,  Andrew Walker ,  Tanmay Kumar

发明人： Michael Konevecki ,  Usha Raghuram ,  Maitreyee Mahajani ,  Sucheta Nallamothu ,  Andrew Walker ,  Tanmay Kumar

IPC分类号： G06K7/10

CPC分类号： H01L27/12 ,  H01L21/28282 ,  H01L21/84 ,  H01L23/535 ,  H01L27/0688 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11551 ,  H01L27/11568 ,  H01L27/11578 ,  H01L29/792 ,  H01L2924/0002 ,  H01L2924/00

摘要： The invention provides for polysilicon vias connecting conductive polysilicon layers formed at different heights. Polysilicon vias are advantageously used in a monolithic three dimensional memory array of charge storage transistors. Polysilicon vias according to the present invention can be used, for example, to connect the channel layer of a first device level of charge storage transistor memory cells to the channel layer of a second device layer of such cells formed above the first device level. Similarly, vias according to the present invention can be used to connect the wordline of a first device level of charge storage transistor memory cells to the channel layer of a second device layer of such cells.

公开(公告)号：US07221588B2

公开(公告)日：2007-05-22

申请号：US10729843

申请日：2003-12-05

申请人： Luca G. Fasoli ,  Roy E. Scheuerlein ,  En-Hsing Chen ,  Sucheta Nallamothu ,  Maitreyee Mahajani ,  Andrew J. Walker

发明人： Luca G. Fasoli ,  Roy E. Scheuerlein ,  En-Hsing Chen ,  Sucheta Nallamothu ,  Maitreyee Mahajani ,  Andrew J. Walker

IPC分类号： G11C11/34

CPC分类号： G11C16/04

摘要： An exemplary NAND string memory array includes at least one plane of memory cells, said memory cells comprising thin film modifiable conductance switch devices and which cells are arranged in a plurality of series-connected NAND strings, and NAND strings including a series select device at each end thereof. Another exemplary NAND string memory array includes a group of more than four adjacent NAND strings within the same memory block each associated with a respective global bit line not shared by the other NAND string of the group. Another exemplary NAND string memory array includes NAND strings on identical pitch as their respective global bit lines.

摘要翻译： 示例性NAND串存储器阵列包括至少一个存储器单元平面，所述存储器单元包括薄膜可修改的电导开关器件，并且哪些单元被布置在多个串联的NAND串中，以及包括每个的串联选择器件的NAND串 结束。 另一示例性的NAND串存储器阵列包括在相同存储器块内的多于四个相邻的NAND串的组，每组相关联的不同于该组的另一个NAND串的相应全局位线。 另一示例性的NAND串存储器阵列包括与它们各自的全局位线相同的音调的NAND串。

公开(公告)号：US07508714B2

公开(公告)日：2009-03-24

申请号：US11751567

申请日：2007-05-21

申请人： Luca G. Fasoli ,  Roy E. Scheuerlein ,  En-Hsing Chen ,  Sucheta Nallamothu ,  Maitreyee Mahajani ,  Andrew J. Walker

发明人： Luca G. Fasoli ,  Roy E. Scheuerlein ,  En-Hsing Chen ,  Sucheta Nallamothu ,  Maitreyee Mahajani ,  Andrew J. Walker

IPC分类号： G11C11/34 ,  G11C16/04

CPC分类号： G11C16/04

摘要： An exemplary NAND string memory array includes at least one plane of memory cells, said memory cells comprising thin film modifiable conductance switch devices and which cells are arranged in a plurality of series-connected NAND strings, said NAND strings including a series select device at each end thereof. Another exemplary NAND string memory array includes a group of more than four adjacent NAND strings within the same memory block each associated with a respective global bit line not shared by the other NAND string of the group. Another exemplary NAND string memory array includes NAND strings on identical pitch as their respective global bit lines.

摘要翻译： 示例性NAND串存储器阵列包括存储器单元的至少一个平面，所述存储器单元包括薄膜可修改的电导开关器件，并且哪些单元被布置在多个串联的NAND串中，所述NAND串包括每个的串联选择器件 结束。 另一示例性的NAND串存储器阵列包括在相同存储器块内的多于四个相邻的NAND串的组，每组相关联的不同于该组的另一个NAND串的相应全局位线。 另一示例性的NAND串存储器阵列包括与它们各自的全局位线相同的音调的NAND串。

公开(公告)号：US06960794B2

公开(公告)日：2005-11-01

申请号：US10334649

申请日：2002-12-31

申请人： Andrew J. Walker ,  S. Brad Herner ,  Maitreyee Mahajani ,  En-Hsing Chen ,  Roy E. Scheuerlein ,  Sucheta Nallamothu ,  Mark Clark

发明人： Andrew J. Walker ,  S. Brad Herner ,  Maitreyee Mahajani ,  En-Hsing Chen ,  Roy E. Scheuerlein ,  Sucheta Nallamothu ,  Mark Clark

IPC分类号： H01L27/12 ,  H01L29/786 ,  H01L29/76

CPC分类号： H01L29/78696 ,  H01L27/12 ,  H01L29/78675

摘要： A thin film transistor with a channel less than 100 angstroms thick, preferably less than 80 angstroms thick, preferably less than 60 angstroms thick. The very thin channel reduces variability of threshold voltage from one TFT to the next. This is particularly advantageous for TFT memory arrays. It is possible that an extremely thin channel restricts the size of grains, forcing many small grains to be formed.

摘要翻译： 一个薄膜晶体管，其通道厚度小于100埃，优选小于80埃，优选小于60埃。 非常薄的通道降低了从一个TFT到下一个TFT的阈值电压的变化。 这对于TFT存储器阵列是特别有利的。 可能的是，极细的通道限制了晶粒的尺寸，迫使许多小晶粒形成。

公开(公告)号：US20050122779A1

公开(公告)日：2005-06-09

申请号：US10729843

申请日：2003-12-05

申请人： Luca Fasoli ,  Roy Scheuerlein ,  En-Hsing Chen ,  Sucheta Nallamothu ,  Maitreyee Mahajani ,  Andrew Walker

发明人： Luca Fasoli ,  Roy Scheuerlein ,  En-Hsing Chen ,  Sucheta Nallamothu ,  Maitreyee Mahajani ,  Andrew Walker

IPC分类号： G11C16/04

CPC分类号： G11C16/04

摘要： An exemplary NAND string memory array includes at least one plane of memory cells, said memory cells comprising thin film modifiable conductance switch devices and which cells are arranged in a plurality of series-connected NAND strings, and NAND strings including a series select device at each end thereof. Another exemplary NAND string memory array includes a group of more than four adjacent NAND strings within the same memory block each associated with a respective global bit line not shared by the other NAND string of the group. Another exemplary NAND string memory array includes NAND strings on identical pitch as their respective global bit lines.

摘要翻译： 示例性NAND串存储器阵列包括至少一个存储器单元平面，所述存储器单元包括薄膜可修改的电导开关器件，并且哪些单元被布置在多个串联的NAND串中，以及包括每个的串联选择器件的NAND串 结束。 另一示例性的NAND串存储器阵列包括在相同存储器块内的多于四个相邻的NAND串的组，每组相关联的不同于该组的另一个NAND串的相应全局位线。 另一示例性的NAND串存储器阵列包括与它们各自的全局位线相同的音调的NAND串。