公开(公告)号：US07508714B2

公开(公告)日：2009-03-24

申请号：US11751567

申请日：2007-05-21

申请人： Luca G. Fasoli ,  Roy E. Scheuerlein ,  En-Hsing Chen ,  Sucheta Nallamothu ,  Maitreyee Mahajani ,  Andrew J. Walker

发明人： Luca G. Fasoli ,  Roy E. Scheuerlein ,  En-Hsing Chen ,  Sucheta Nallamothu ,  Maitreyee Mahajani ,  Andrew J. Walker

IPC分类号： G11C11/34 ,  G11C16/04

CPC分类号： G11C16/04

摘要： An exemplary NAND string memory array includes at least one plane of memory cells, said memory cells comprising thin film modifiable conductance switch devices and which cells are arranged in a plurality of series-connected NAND strings, said NAND strings including a series select device at each end thereof. Another exemplary NAND string memory array includes a group of more than four adjacent NAND strings within the same memory block each associated with a respective global bit line not shared by the other NAND string of the group. Another exemplary NAND string memory array includes NAND strings on identical pitch as their respective global bit lines.

摘要翻译： 示例性NAND串存储器阵列包括存储器单元的至少一个平面，所述存储器单元包括薄膜可修改的电导开关器件，并且哪些单元被布置在多个串联的NAND串中，所述NAND串包括每个的串联选择器件 结束。 另一示例性的NAND串存储器阵列包括在相同存储器块内的多于四个相邻的NAND串的组，每组相关联的不同于该组的另一个NAND串的相应全局位线。 另一示例性的NAND串存储器阵列包括与它们各自的全局位线相同的音调的NAND串。

公开(公告)号：US07221588B2

公开(公告)日：2007-05-22

申请号：US10729843

申请日：2003-12-05

申请人： Luca G. Fasoli ,  Roy E. Scheuerlein ,  En-Hsing Chen ,  Sucheta Nallamothu ,  Maitreyee Mahajani ,  Andrew J. Walker

发明人： Luca G. Fasoli ,  Roy E. Scheuerlein ,  En-Hsing Chen ,  Sucheta Nallamothu ,  Maitreyee Mahajani ,  Andrew J. Walker

IPC分类号： G11C11/34

CPC分类号： G11C16/04

摘要： An exemplary NAND string memory array includes at least one plane of memory cells, said memory cells comprising thin film modifiable conductance switch devices and which cells are arranged in a plurality of series-connected NAND strings, and NAND strings including a series select device at each end thereof. Another exemplary NAND string memory array includes a group of more than four adjacent NAND strings within the same memory block each associated with a respective global bit line not shared by the other NAND string of the group. Another exemplary NAND string memory array includes NAND strings on identical pitch as their respective global bit lines.

摘要翻译： 示例性NAND串存储器阵列包括至少一个存储器单元平面，所述存储器单元包括薄膜可修改的电导开关器件，并且哪些单元被布置在多个串联的NAND串中，以及包括每个的串联选择器件的NAND串 结束。 另一示例性的NAND串存储器阵列包括在相同存储器块内的多于四个相邻的NAND串的组，每组相关联的不同于该组的另一个NAND串的相应全局位线。 另一示例性的NAND串存储器阵列包括与它们各自的全局位线相同的音调的NAND串。

公开(公告)号：US07233522B2

公开(公告)日：2007-06-19

申请号：US10729831

申请日：2003-12-05

申请人： En-Hsing Chen ,  Andrew J. Walker ,  Roy E. Scheuerlein ,  Sucheta Nallamothu ,  Alper Ilkbahar ,  Luca G. Fasoli

发明人： En-Hsing Chen ,  Andrew J. Walker ,  Roy E. Scheuerlein ,  Sucheta Nallamothu ,  Alper Ilkbahar ,  Luca G. Fasoli

IPC分类号： G11C16/04

CPC分类号： G11C16/3418 ,  G11C11/5621 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/3427 ,  H01L27/115 ,  H01L27/11568 ,  H01L27/1159

摘要： An exemplary NAND string memory array provides for capacitive boosting of a half-selected memory cell channel to reduce program disturb effects of the half selected cell. To reduce the effect of leakage current degradation of the boosted level, multiple programming pulses of a shorter duration are employed to limit the time period during which such leakage currents may degrade the voltage within the unselected NAND strings. In addition, multiple series select devices at one or both ends of each NAND string further ensure reduced leakage through such select devices, for both unselected and selected NAND strings. In certain exemplary embodiments, a memory array includes series-connected NAND strings of memory cell transistors having a charge storage dielectric, and includes more than one plane of memory cells formed above a substrate.

摘要翻译： 示例性的NAND串存储器阵列提供半选择的存储器单元通道的电容性升压以减少半选择单元的程序干扰效应。 为了减小升压电平的漏电流劣化的影响，采用较短持续时间的多个编程脉冲来限制这种漏电流可能降低未选择的NAND串中的电压的时间周期。 此外，在每个NAND串的一端或两端的多个串联选择装置进一步确保了对于未选择的和选择的NAND串的这种选择装置的减少的泄漏。 在某些示例性实施例中，存储器阵列包括具有电荷存储电介质的存储单元晶体管的串联连接的NAND串，并且包括形成在衬底上方的多于一个的存储单元平面。

公开(公告)号：US07433233B2

公开(公告)日：2008-10-07

申请号：US11764793

申请日：2007-06-18

申请人： En-Hsing Chen ,  Andrew J. Walker ,  Roy E. Scheuerlein ,  Sucheta Nallamothu ,  Alper Ilkbahar ,  Luca G. Fasoli

发明人： En-Hsing Chen ,  Andrew J. Walker ,  Roy E. Scheuerlein ,  Sucheta Nallamothu ,  Alper Ilkbahar ,  Luca G. Fasoli

IPC分类号： G11C11/34 ,  G11C16/04

CPC分类号： G11C16/3418 ,  G11C11/5621 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/3427 ,  H01L27/115 ,  H01L27/11568 ,  H01L27/1159

摘要： An exemplary NAND string memory array provides for capacitive boosting of a half-selected memory cell channel to reduce program disturb effects of the half selected cell. To reduce the effect of leakage current degradation of the boosted level, multiple programming pulses of a shorter duration are employed to limit the time period during which such leakage currents may degrade the voltage within the unselected NAND strings. In addition, multiple series select devices at one or both ends of each NAND string further ensure reduced leakage through such select devices, for both unselected and selected NAND strings. In certain exemplary embodiments, a memory array includes series-connected NAND strings of memory cell transistors having a charge storage dielectric, and includes more than one plane of memory cells formed above a substrate.

摘要翻译： 示例性的NAND串存储器阵列提供半选择的存储器单元通道的电容性升压以减少半选择单元的程序干扰效应。 为了减小升压电平的漏电流劣化的影响，采用较短持续时间的多个编程脉冲来限制这种漏电流可能降低未选择的NAND串中的电压的时间周期。 此外，在每个NAND串的一端或两端的多个串联选择装置进一步确保了对于未选择的和选择的NAND串的这种选择装置的减少的泄漏。 在某些示例性实施例中，存储器阵列包括具有电荷存储电介质的存储单元晶体管的串联连接的NAND串，并且包括形成在衬底上方的多于一个的存储单元平面。

公开(公告)号：US07023739B2

公开(公告)日：2006-04-04

申请号：US10729844

申请日：2003-12-05

申请人： En-Hsing Chen ,  Andrew J. Walker ,  Roy E. Scheuerlein ,  Sucheta Nallamothu ,  Alper Ilkbahar ,  Luca G. Fasoli

发明人： En-Hsing Chen ,  Andrew J. Walker ,  Roy E. Scheuerlein ,  Sucheta Nallamothu ,  Alper Ilkbahar ,  Luca G. Fasoli

IPC分类号： G11C16/04 ,  G11C16/06

CPC分类号： G11C16/10 ,  G11C11/5671 ,  G11C16/0466 ,  G11C16/0483

摘要： An exemplary NAND string memory array provides for capacitive boosting of a half-selected memory cell channel to reduce program disturb effects of the half selected cell. To reduce the effect of leakage current degradation of the boosted level, multiple programming pulses of a shorter duration are employed to limit the time period during which such leakage currents may degrade the voltage within the unselected NAND strings. In addition, multiple series select devices at one or both ends of each NAND string further ensure reduced leakage through such select devices, for both unselected and selected NAND strings. In certain exemplary embodiments, a memory array includes series-connected NAND strings of memory cell transistors having a charge storage dielectric, and includes more than one plane of memory cells formed above a substrate.

摘要翻译： 示例性的NAND串存储器阵列提供半选择的存储器单元通道的电容性升压以减少半选择单元的程序干扰效应。 为了减小升压电平的漏电流劣化的影响，采用较短持续时间的多个编程脉冲来限制这种漏电流可能降低未选择的NAND串中的电压的时间周期。 此外，在每个NAND串的一端或两端的多个串联选择装置进一步确保了对于未选择的和选择的NAND串的这种选择装置的减少的泄漏。 在某些示例性实施例中，存储器阵列包括具有电荷存储电介质的存储单元晶体管的串联连接的NAND串，并且包括形成在衬底上方的多于一个的存储单元平面。

公开(公告)号：US08279704B2

公开(公告)日：2012-10-02

申请号：US12895523

申请日：2010-09-30

申请人： Roy E. Scheuerlein ,  Luca G. Fasoli

发明人： Roy E. Scheuerlein ,  Luca G. Fasoli

IPC分类号： G11C8/00

CPC分类号： G11C7/18 ,  G11C7/1048 ,  G11C8/08 ,  G11C8/12 ,  G11C8/14

摘要： Circuits and methods are described for decoding exemplary memory arrays of programmable and, in some embodiments, re-writable passive element memory cells, which are particularly useful for extremely dense three-dimensional memory arrays having more than one memory plane. In addition, circuits and methods are described for selecting one or more array blocks of such a memory array, for selecting one or more word lines and bit lines within selected array blocks, for conveying data information to and from selected memory cells within selected array blocks, and for conveying unselected bias conditions to unselected array blocks.

摘要翻译： 描述了用于解码可编程的示例性存储器阵列的电路和方法，在一些实施例中，可重写无源元件存储器单元，其对于具有多于一个存储器平面的非常密集的三维存储器阵列特别有用。 此外，描述了用于选择这种存储器阵列的一个或多个阵列块的电路和方法，用于选择所选择的阵列块内的一个或多个字线和位线，用于将数据信息传送到选定的阵列块内的选定的存储器单元 并且用于将未选择的偏置条件传送到未选择的阵列块。

公开(公告)号：US08059447B2

公开(公告)日：2011-11-15

申请号：US12339338

申请日：2008-12-19

申请人： Roy E. Scheuerlein ,  Luca G. Fasoli ,  Tianhong Yan

发明人： Roy E. Scheuerlein ,  Luca G. Fasoli ,  Tianhong Yan

IPC分类号： G11C11/00

CPC分类号： G11C13/0007 ,  G11C7/12 ,  G11C7/22 ,  G11C13/0026 ,  G11C13/0064 ,  G11C13/0069 ,  G11C2013/009 ,  G11C2213/32 ,  G11C2213/34 ,  G11C2213/71

摘要： A memory system includes a substrate, control circuitry on the substrate, a three dimensional memory array (above the substrate) that includes a plurality of memory cells with reversible resistance-switching elements, and circuits for limiting the SET current for the reversible resistance-switching elements. The circuits for limiting the SET current provide a charge on one or more bit lines that is not sufficient to SET the memory cells, and then discharge the bit lines through the memory cells in order to SET the memory cells.

摘要翻译： 存储器系统包括衬底，衬底上的控制电路，包括具有可逆电阻切换元件的多个存储器单元的三维存储器阵列（衬底上方），以及用于限制用于可逆电阻切换的SET电流的电路 元素。 用于限制SET电流的电路在不足以设置存储器单元的一个或多个位线上提供电荷，然后通过存储器单元放电位线以设置存储器单元。

公开(公告)号：US07554832B2

公开(公告)日：2009-06-30

申请号：US11461339

申请日：2006-07-31

申请人： Luca G. Fasoli ,  Christopher J. Petti ,  Roy E. Scheuerlein

发明人： Luca G. Fasoli ,  Christopher J. Petti ,  Roy E. Scheuerlein

IPC分类号： G11C11/00

CPC分类号： G11C8/14

摘要： Circuits and methods are described for decoding exemplary memory arrays of programmable and, in some embodiments, re-writable passive element memory cells, which are particularly useful for extremely dense three-dimensional memory arrays having more thane one memory plane. In addition, circuits and methods are described for selecting one or more array blocks of such a memory array, for selecting one or more word lines and bit lines within selected array blocks, for conveying data information to and from selected memory cells within selected array blocks, and for conveying unselected bias conditions to unselected array blocks.

摘要翻译： 描述了用于解码可编程的示例性存储器阵列的电路和方法，在一些实施例中，可重写无源元件存储器单元，其对于具有多于一个存储器平面的非常密集的三维存储器阵列特别有用。 此外，描述了用于选择这种存储器阵列的一个或多个阵列块的电路和方法，用于选择所选择的阵列块内的一个或多个字线和位线，用于将数据信息传送到选定的阵列块内的选定的存储器单元 并且用于将未选择的偏置条件传送到未选择的阵列块。

公开(公告)号：US20090161474A1

公开(公告)日：2009-06-25

申请号：US12396461

申请日：2009-03-02

申请人： Roy E. Scheuerlein ,  Luca G. Fasoli

发明人： Roy E. Scheuerlein ,  Luca G. Fasoli

IPC分类号： G11C8/10 ,  G11C8/08 ,  H01S4/00

CPC分类号： G11C8/12 ,  G11C7/1048 ,  G11C7/18 ,  G11C8/08 ,  G11C8/14 ,  Y10T29/49002

摘要： Circuits and methods are described for decoding exemplary memory arrays of programmable and, in some embodiments, re-writable passive element memory cells, which are particularly useful for extremely dense three-dimensional memory arrays having more than one memory plane. In addition, circuits and methods are described for selecting one or more array blocks of such a memory array, for selecting one or more word lines and bit lines within selected array blocks, for conveying data information to and from selected memory cells within selected array blocks, and for conveying unselected bias conditions to unselected array blocks.

摘要翻译： 描述了用于解码可编程的示例性存储器阵列的电路和方法，在一些实施例中，可重写无源元件存储器单元，其对于具有多于一个存储器平面的非常密集的三维存储器阵列特别有用。 此外，描述了用于选择这种存储器阵列的一个或多个阵列块的电路和方法，用于选择所选择的阵列块内的一个或多个字线和位线，用于将数据信息传送到选定的阵列块内的选定的存储器单元 并且用于将未选择的偏置条件传送到未选择的阵列块。

公开(公告)号：US07542370B2

公开(公告)日：2009-06-02

申请号：US11618844

申请日：2006-12-31

申请人： Tianhong Yan ,  Luca G. Fasoli ,  Roy E. Scheuerlein

发明人： Tianhong Yan ,  Luca G. Fasoli ,  Roy E. Scheuerlein

IPC分类号： G11C8/00

CPC分类号： G11C8/10 ,  G11C8/08 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0011 ,  G11C13/0014 ,  G11C13/0016 ,  G11C13/0028 ,  G11C17/16 ,  G11C17/165 ,  G11C2213/31 ,  G11C2213/32 ,  G11C2213/35

摘要： A reversible polarity decoder circuit is disclosed which is particularly suitable for implementing a multi-headed decoder structure, such as might be used for decoding word lines, and particularly in a 3D memory array. The decoder circuit provides an overdrive voltage bias to the gates of half-selected word line driver circuits to solidly maintain the half-selected word lines at an inactive level. If the memory array is biased at or near the breakdown voltage, this overdrive voltage may be greater than the breakdown voltage of the decoder transistors. However, in the embodiments described, the decoder circuit accomplishes this without impressing a voltage greater than the breakdown voltage across any of the decoder transistors, for either polarity of operation of the decoder circuit.

摘要翻译： 公开了一种可逆极性解码器电路，其特别适用于实现多头解码器结构，例如可用于解码字线，特别是在3D存储器阵列中。 解码器电路向半选择的字线驱动电路的栅极提供过驱动电压偏置，以将半选择的字线牢固地保持在非活动电平。 如果存储器阵列被偏置在或接近击穿电压，则该过驱动电压可能大于解码晶体管的击穿电压。 然而，在所描述的实施例中，解码器电路实现这一点，而不会对解码器电路的任一极性进行施加大于任何解码晶体管的击穿电压的电压。