Common Mode Sensing Architecture
    1.
    发明申请

    公开(公告)号:US20190222185A1

    公开(公告)日:2019-07-18

    申请号:US15940709

    申请日:2018-03-29

    Abstract: An amplifier includes a differential positive input, a differential negative input, and a transistor. The transistor is communicatively coupled to the differential positive input and differential negative input at a source of the transistor. The transistor is configured to track input common mode of the differential positive input and differential negative input.

    Current sense amplifier architecture and level shifter

    公开(公告)号:US10564186B2

    公开(公告)日:2020-02-18

    申请号:US15712771

    申请日:2017-09-22

    Abstract: A high side current sensing amplifier architecture is simplified and improved over prior art current sensing amplifier circuits by using chopping only, without requiring auto-zeroing, and by using a simpler (and faster) switched capacitor filter instead of an auto-zeroing integrator filter. Also, VIP (positive DC sense node) is merged with the VDDHV (power supply) node, such that the integrated circuit package requires only a single node (package pin) to accommodate both the VIP and VDDHV connections for the current sensing amplifier circuit, resulting in being able to use a smaller integrated circuit package. A small resistor is coupled between VIP and VDDHV to reduce the offset considerably. A low latency time high voltage level shifter is provided which is essential for precise chopping operation.

    SWITCHED CAPACITORS TO GALVANICALLY ISOLATE AND AMPLIFY ANALOG SIGNALS VIA TRANSFERRED DIFFERENTIAL VOLTAGE SIGNAL

    公开(公告)号:US20240405730A1

    公开(公告)日:2024-12-05

    申请号:US18658240

    申请日:2024-05-08

    Abstract: Integrated circuits and methods to provide an operative coupling comprising an input stage and an output stage between an analog input and an analog output; synchronously operate a plurality of high voltage domain switches of the input stage and a plurality of low voltage domain switches of the output stage at a frequency to galvanically isolate the input stage from the output stage across a plurality of capacitors having a plurality of input plates respectively connected to the switches of the input and output stages; supply an analog input signal to the input stage; transfer a differential voltage signal component within a range of a common mode voltage supply from the high voltage domain of the input stage to the low voltage domain of the output stage; differentially amplify the low voltage domain differential voltage signal component; and output an analog output signal.

    DEVICE AND SYSTEM FOR ESD PROTECTION
    6.
    发明公开

    公开(公告)号:US20240355809A1

    公开(公告)日:2024-10-24

    申请号:US18520616

    申请日:2023-11-28

    CPC classification number: H01L27/0266 H01L27/0292

    Abstract: A circuit for electrostatic discharge (ESD) protection may protect sensitive circuits in the presence of both positive and negative ESD events. A protection transistor may be coupled to a pad, and a protection clamp may be coupled to the protection transistor. The protection transistor may be in an isolation n-well, and a current limiting resistor may be coupled from the pad to the isolation n-well. In operation, the current limiting resistor may limit the current during negative ESD events.

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