公开(公告)号：US10002103B2

公开(公告)日：2018-06-19

申请号：US15065027

申请日：2016-03-09

Applicant: Microchip Technology Incorporated

Inventor： Bryan Kris ,  Igor Wojewoda ,  Alex Dumais ,  Mike Catherwood ,  Brian Fall ,  Jason Tollefson ,  Calum Wilke ,  Dave Mickey ,  Thomas Spohrer ,  Jim Pepping ,  Vincent Sheard

IPC: G06F13/00 ,  G06F3/00 ,  G06F13/42 ,  G06F13/364 ,  G06F13/16 ,  G06F13/38 ,  G06F15/167 ,  G06F1/22

CPC classification number: G06F13/4282 ,  G06F1/22 ,  G06F13/1673 ,  G06F13/364 ,  G06F13/385 ,  G06F15/167 ,  Y02D10/14 ,  Y02D10/151

Abstract: A microcontroller device has a housing with a plurality of external pins a first microcontroller with a first central processing unit (CPU), a first system bus coupled with the first CPU, first memory coupled with the first system bus, and a first plurality of peripheral devices coupled with the first system bus, and a second microcontroller with a second central processing unit (CPU), a second system bus coupled with the second CPU, second memory coupled with the second system bus, and a second plurality of peripheral devices coupled with the second system bus, wherein first and second microcontroller communicate only via a dedicated interface.

公开(公告)号：US20160267047A1

公开(公告)日：2016-09-15

申请号：US15065027

申请日：2016-03-09

Applicant: Microchip Technology Incorporated

Inventor： Bryan Kris ,  Igor Wojewoda ,  Alex Dumais ,  Mike Catherwood ,  Brian Fall ,  Jason Tollefson ,  Calum Wilke ,  Dave Mickey ,  Thomas Spohrer ,  Jim Pepping ,  Vincent Sheard

IPC: G06F13/42 ,  G06F13/16 ,  G06F13/364

CPC classification number: G06F13/4282 ,  G06F1/22 ,  G06F13/1673 ,  G06F13/364 ,  G06F13/385 ,  G06F15/167 ,  Y02D10/14 ,  Y02D10/151

Abstract: A microcontroller device has a housing with a plurality of external pins a first microcontroller with a first central processing unit (CPU), a first system bus coupled with the first CPU, first memory coupled with the first system bus, and a first plurality of peripheral devices coupled with the first system bus, and a second microcontroller with a second central processing unit (CPU), a second system bus coupled with the second CPU, second memory coupled with the second system bus, and a second plurality of peripheral devices coupled with the second system bus, wherein first and second microcontroller communicate only via a dedicated interface.

Abstract translation: 微控制器装置具有壳体，其具有多个外部引脚，第一微控制器具有第一中央处理单元（CPU），与第一CPU耦合的第一系统总线，与第一系统总线耦合的第一存储器和第一多个外设 与第一系统总线耦合的设备，以及具有第二中央处理单元（CPU）的第二微控制器，与第二CPU耦合的第二系统总线，与第二系统总线耦合的第二存储器以及与第二系统总线耦合的第二多个外围设备 第二系统总线，其中第一和第二微控制器仅通过专用接口进行通信。