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公开(公告)号：US10102050B2
公开(公告)日：2018-10-16
申请号：US15012287
申请日：2016-02-01
发明人： Bryan Kris , Mike Catherwood , Dave Mickey , Brian Fall , Calum Wilkie , Vincent Sheard , Alex Dumais
IPC分类号： G06F11/07 , G06F11/22 , G01R31/28 , G06F11/36 , G01R31/3177
摘要： In a debugging method for an integrated circuit device which has multiple processing cores, a debugging breakpoint is activated at a first processor core in the integrated circuit device. Upon activation, the debugging breakpoint stops execution of instructions in the first processor core and the debugging breakpoint is communicated to a second processor core in the integrated circuit device.
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2.发明申请公开(公告)号：US20160267046A1
公开(公告)日：2016-09-15
申请号：US15064964
申请日：2016-03-09
发明人： Bryan Kris , Igor Wojewoda , Alex Dumais , Mike Catherwood , Brian Fall , Jason Tollefson , Calum Wilke , Dave Mickey , Thomas Spohrer
IPC分类号： G06F13/42 , G06F13/16 , G06F13/364
CPC分类号： G06F13/4282 , G06F13/1673 , G06F13/364 , G06F13/385 , G06F15/7807 , Y02D10/12 , Y02D10/13 , Y02D10/14 , Y02D10/151
摘要： A microcontroller device has a housing with a plurality of external pins having a plurality of input/output pins, a first microcontroller with a first central processing unit (CPU), a first system bus coupled with the first CPU, first memory coupled with the first system bus, and a first plurality of peripheral devices coupled with the first system bus, a second microcontroller with a second central processing unit (CPU), a second system bus coupled with the second CPU, second memory coupled with the second system bus, and a second plurality of peripheral devices coupled with the second system bus, and a pad ownership multiplexer unit being controllable to assign control of the input/output pins to either the first microcontroller or the second microcontroller, wherein the number of external pins is less than the sum of a data buswidth of the first and second microcontroller.
摘要翻译： 微控制器装置具有壳体，多个外部引脚具有多个输入/输出引脚，具有第一中央处理单元（CPU）的第一微控制器，与第一CPU耦合的第一系统总线，与第一中央处理单元 系统总线和与第一系统总线耦合的第一多个外围设备，具有第二中央处理单元（CPU）的第二微控制器，与第二CPU耦合的第二系统总线，与第二系统总线耦合的第二存储器，以及 与第二系统总线耦合的第二多个外围设备，以及焊盘所有权复用器单元，其可控制以将输入/输出引脚的控制分配给第一微控制器或第二微控制器，其中外部引脚的数量小于 第一和第二微控制器的数据总线宽度之和。
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公开(公告)号：US10002103B2
公开(公告)日：2018-06-19
申请号：US15065027
申请日：2016-03-09
发明人： Bryan Kris , Igor Wojewoda , Alex Dumais , Mike Catherwood , Brian Fall , Jason Tollefson , Calum Wilke , Dave Mickey , Thomas Spohrer , Jim Pepping , Vincent Sheard
IPC分类号： G06F13/00 , G06F3/00 , G06F13/42 , G06F13/364 , G06F13/16 , G06F13/38 , G06F15/167 , G06F1/22
CPC分类号： G06F13/4282 , G06F1/22 , G06F13/1673 , G06F13/364 , G06F13/385 , G06F15/167 , Y02D10/14 , Y02D10/151
摘要： A microcontroller device has a housing with a plurality of external pins a first microcontroller with a first central processing unit (CPU), a first system bus coupled with the first CPU, first memory coupled with the first system bus, and a first plurality of peripheral devices coupled with the first system bus, and a second microcontroller with a second central processing unit (CPU), a second system bus coupled with the second CPU, second memory coupled with the second system bus, and a second plurality of peripheral devices coupled with the second system bus, wherein first and second microcontroller communicate only via a dedicated interface.
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公开(公告)号：US10002102B2
公开(公告)日：2018-06-19
申请号：US15064964
申请日：2016-03-09
发明人： Bryan Kris , Igor Wojewoda , Alex Dumais , Mike Catherwood , Brian Fall , Jason Tollefson , Calum Wilke , Dave Mickey , Thomas Spohrer
CPC分类号： G06F13/4282 , G06F13/1673 , G06F13/364 , G06F13/385 , G06F15/7807 , Y02D10/12 , Y02D10/13 , Y02D10/14 , Y02D10/151
摘要： A microcontroller device has a housing with a plurality of external pins having a plurality of input/output pins, a first microcontroller with a first central processing unit (CPU), a first system bus coupled with the first CPU, first memory coupled with the first system bus, and a first plurality of peripheral devices coupled with the first system bus, a second microcontroller with a second central processing unit (CPU), a second system bus coupled with the second CPU, second memory coupled with the second system bus, and a second plurality of peripheral devices coupled with the second system bus, and a pad ownership multiplexer unit being controllable to assign control of the input/output pins to either the first microcontroller or the second microcontroller, wherein the number of external pins is less than the sum of a data buswidth of the first and second microcontroller.
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5.发明申请公开(公告)号：US20160267047A1
公开(公告)日：2016-09-15
申请号：US15065027
申请日：2016-03-09
发明人： Bryan Kris , Igor Wojewoda , Alex Dumais , Mike Catherwood , Brian Fall , Jason Tollefson , Calum Wilke , Dave Mickey , Thomas Spohrer , Jim Pepping , Vincent Sheard
IPC分类号： G06F13/42 , G06F13/16 , G06F13/364
CPC分类号： G06F13/4282 , G06F1/22 , G06F13/1673 , G06F13/364 , G06F13/385 , G06F15/167 , Y02D10/14 , Y02D10/151
摘要： A microcontroller device has a housing with a plurality of external pins a first microcontroller with a first central processing unit (CPU), a first system bus coupled with the first CPU, first memory coupled with the first system bus, and a first plurality of peripheral devices coupled with the first system bus, and a second microcontroller with a second central processing unit (CPU), a second system bus coupled with the second CPU, second memory coupled with the second system bus, and a second plurality of peripheral devices coupled with the second system bus, wherein first and second microcontroller communicate only via a dedicated interface.
摘要翻译： 微控制器装置具有壳体，其具有多个外部引脚，第一微控制器具有第一中央处理单元（CPU），与第一CPU耦合的第一系统总线，与第一系统总线耦合的第一存储器和第一多个外设 与第一系统总线耦合的设备，以及具有第二中央处理单元（CPU）的第二微控制器，与第二CPU耦合的第二系统总线，与第二系统总线耦合的第二存储器以及与第二系统总线耦合的第二多个外围设备 第二系统总线，其中第一和第二微控制器仅通过专用接口进行通信。
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