公开(公告)号：US20170017584A1

公开(公告)日：2017-01-19

申请号：US15209467

申请日：2016-07-13

Applicant: Microchip Technology Incorporated

Inventor： Kevin Kilzer ,  Shyamsunder Ramanathan ,  Sai Karthik Rajaraman ,  Justin Milks

IPC: G06F13/10 ,  G06F13/40 ,  G06F13/42 ,  G06F13/16

CPC classification number: G06F13/102 ,  G06F13/1673 ,  G06F13/1689 ,  G06F13/4068 ,  G06F13/4282 ,  G06F13/4291

Abstract: A synchronous serial peripheral device has a transmission unit coupled with a data output line and a clock unit coupled with a clock line. The serial peripheral device transmits a minimum of a single transmission, wherein in a first operating mode the transmission unit and the clock unit are configurable to perform a data transmission with a data length that can be defined to be between one (1) and eight (8) bit.

Abstract translation: 同步串行外围设备具有与数据输出线耦合的传输单元和与时钟线耦合的时钟单元。 串行外围设备发送最少的单个传输，其中在第一操作模式中，传输单元和时钟单元可配置为执行具有数据长度的数据传输，数据长度可以被定义在1（1）到8（ 8）位。

公开(公告)号：US20170168980A1

公开(公告)日：2017-06-15

申请号：US15373219

申请日：2016-12-08

Applicant: Microchip Technology Incorporated

Inventor： Kevin Kilzer ,  Shyamsunder Ramanathan ,  Sai Karthik Rajaraman ,  Justin Milks

IPC: G06F13/42 ,  G06F1/10

CPC classification number: G06F13/4282 ,  G06F1/10 ,  G06F13/4291

Abstract: A serial peripheral interface (SPI) module, comprising a transceiver, the transceiver including a clock line, a data line and at least one slave select line. The SPI also comprises an interface circuit configured to operate in an automatic slave select mode, wherein the interface circuit is configured to automatically assert the slave select line at least one clock before a first clock edge is generated.

公开(公告)号：US20170168981A1

公开(公告)日：2017-06-15

申请号：US15373391

申请日：2016-12-08

Applicant: Microchip Technology Incorporated

Inventor： Kevin Kilzer ,  Shyamsunder Ramanathan ,  Sai Karthik Rajaraman ,  Justin Milks

IPC: G06F13/42 ,  G06F13/40 ,  G06F13/364

CPC classification number: G06F13/4282 ,  G06F13/364 ,  G06F13/404 ,  G06F13/4291

Abstract: A serial peripheral interface (SPI) module includes a transceiver including a clock line, a data line and at least one slave select line. The module also includes an interface circuit configured to monitor the slave select line and assert a fault based upon an incorrect de-assertion of the slave select line.