公开(公告)号：US20240234351A9

公开(公告)日：2024-07-11

申请号：US18348365

申请日：2023-07-07

Applicant: National Yang Ming Chiao Tung University

Inventor： Chih CHEN ,  Shih-Chi YANG

IPC: H01L23/00 ,  H01L25/065

CPC classification number: H01L24/08 ,  H01L24/03 ,  H01L24/05 ,  H01L24/80 ,  H01L25/0657 ,  H01L2224/02165 ,  H01L2224/03462 ,  H01L2224/05647 ,  H01L2224/0801 ,  H01L2224/08121 ,  H01L2224/08148 ,  H01L2224/80895 ,  H01L2225/06524 ,  H01L2924/2064

Abstract: An electrical connection includes a first driving substrate, a first adhesive layer, a first bonding pad a first bonding pad and a second bonding pad. The first driving substrate includes a first substrate and a first dielectric layer on the first substrate. The first adhesive layer is at a sidewall of the first dielectric layer of the first driving substrate. The first bonding pad is on the first substrate of the first driving substrate and in contact with the first adhesive layer, and the first bonding pad includes a plurality of grains, the grains are connected with each other, the grains include [111]-oriented copper grains, and a maximum width of the first bonding pad is equal to or less than 8 microns. The second bonding pad is on the first bonding pad.

公开(公告)号：US20240186269A1

公开(公告)日：2024-06-06

申请号：US18061383

申请日：2022-12-02

Applicant: ADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC.

Inventor： Belgacem Haba

IPC: H01L23/00 ,  H01L23/552 ,  H01L25/065

CPC classification number: H01L23/573 ,  H01L23/552 ,  H01L24/08 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L24/80 ,  H01L25/0657 ,  H01L2224/0801 ,  H01L2224/08057 ,  H01L2224/08145 ,  H01L2224/16221 ,  H01L2224/32221 ,  H01L2224/73204 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2225/06517 ,  H01L2225/06524 ,  H01L2225/06568 ,  H01L2924/1431 ,  H01L2924/1434

Abstract: A bonded structure is disclosed. The bonded structure can comprise a semiconductor element comprising active circuitry and a security die electrically connected and directly bonded to a surface of the semiconductor element without an adhesive along a bonding interface. The security die can include a security core. The security core can contain an encryption logic and a memory. The security core can be configured to decrypt data to be transferred to the active circuitry and to encrypt signals from the active circuitry.

公开(公告)号：US20240170350A1

公开(公告)日：2024-05-23

申请号：US18150574

申请日：2023-01-05

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Shih-Wei LIANG ,  Nien-Fang WU ,  Jiun-Yi WU

IPC: H01L23/10 ,  H01L21/48 ,  H01L23/00 ,  H01L25/065

CPC classification number: H01L23/10 ,  H01L21/4817 ,  H01L24/03 ,  H01L24/08 ,  H01L24/09 ,  H01L24/80 ,  H01L24/94 ,  H01L25/0657 ,  H01L2224/03616 ,  H01L2224/0801 ,  H01L2224/08059 ,  H01L2224/08145 ,  H01L2224/0903 ,  H01L2224/09051 ,  H01L2224/09517 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2224/94 ,  H01L2225/06524 ,  H01L2225/06527 ,  H01L2924/3512

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate having a device region and a seal ring region surrounding the device region. The semiconductor device structure includes a seal ring structure over the seal ring region. The seal ring structure surrounds the device region. The semiconductor device structure includes a bonding film over the seal ring structure and the substrate. The semiconductor device structure includes a bonding pad embedded in the bonding film. The bonding pad overlaps the seal ring structure along an axis perpendicular to a first top surface of the substrate, and a second top surface of the bonding pad is substantially level with a third top surface of the bonding film.

公开(公告)号：US20240055379A1

公开(公告)日：2024-02-15

申请号：US18140960

申请日：2023-04-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： HASEOB SEONG ,  AENEE JANG

IPC: H01L23/00 ,  H10B80/00 ,  H01L25/065

CPC classification number: H01L24/08 ,  H10B80/00 ,  H01L24/05 ,  H01L24/80 ,  H01L24/94 ,  H01L25/0657 ,  H01L2225/06593 ,  H01L2225/06541 ,  H01L2224/94 ,  H01L2224/05647 ,  H01L2224/05687 ,  H01L2224/8013 ,  H01L2224/80203 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2224/08145 ,  H01L2224/0213 ,  H01L2224/0214 ,  H01L2224/02145 ,  H01L2224/0215 ,  H01L2224/0801 ,  H01L2924/16235 ,  H01L2924/1616

Abstract: A semiconductor package includes; a first semiconductor chip and a second semiconductor chip stacked on the first semiconductor chip. The first semiconductor chip includes; a first substrate, a first bonding pad on a first surface of the first substrate, and a first passivation layer on the first surface of the first substrate exposing at least a portion of the first bonding pad. The second semiconductor chip includes; a second substrate, a second insulation layer on a front surface of the second substrate, a second bonding pad on the second insulation layer, a first alignment key pattern on the second insulation layer, and a second passivation layer on the second insulation layer, covering at least a portion of the first alignment key pattern, and exposing at least a portion of the second bonding pad, wherein the first bonding pad and the second bonding pad are directly bonded, and the first passivation layer and the second passivation layer are directly bonded.

公开(公告)号：US20240030266A1

公开(公告)日：2024-01-25

申请号：US18064134

申请日：2022-12-09

Applicant: SK hynix Inc.

Inventor： Pyong Su KWAG

IPC: H01L27/146 ,  H01L25/065 ,  H01L23/00

CPC classification number: H01L27/14636 ,  H01L25/0657 ,  H01L27/14634 ,  H01L24/08 ,  H01L24/09 ,  H01L2225/06524 ,  H01L2225/06544 ,  H01L2224/0801 ,  H01L2224/08145 ,  H01L2224/0903 ,  H01L2224/09515 ,  H01L2924/1431 ,  H01L2224/02371 ,  H01L2224/02381

Abstract: A stacked semiconductor device may include a first semiconductor chip including a first bonded surface and a second semiconductor chip including a second bonded surface facing the first bonded surface, the first and second bonded surfaces being bonded to each other. The first semiconductor chip includes a first substrate, at least one first power interconnect disposed between the first substrate and the first bonded surface of the first semiconductor chip and configured to carry a power-supply voltage therethrough, and at least one first power hybrid bonding structure disposed to be in contact with the first power interconnect and configured to extend along the same path as a routing path of the first power interconnect. The second semiconductor chip includes a second substrate, at least one second power interconnect disposed between the second bonded surface and the second substrate and configured to carry a power-supply voltage therethrough, and at least one second power hybrid bonding structure disposed to be in contact with the second power interconnect and the first power hybrid bonding structure and configured to extend along the same path as a routing path of the second power interconnect.

公开(公告)号：US20230411328A1

公开(公告)日：2023-12-21

申请号：US18060036

申请日：2022-11-30

Applicant: Kioxia Corporation

Inventor： Shinya ARAI ,  Yuta TAGUCHI

IPC: H01L23/00 ,  H01L25/065

CPC classification number: H01L24/09 ,  H01L24/08 ,  H01L25/0657 ,  H01L2924/1431 ,  H01L2924/1438 ,  H01L2225/06524 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06593 ,  H01L2224/08145 ,  H01L2224/09515 ,  H01L2924/30205 ,  H01L2224/08055 ,  H01L2224/0801 ,  H01L2224/0903 ,  H01L2224/09051 ,  H01L2224/09179 ,  H01L2224/09132 ,  H01L2224/09133

Abstract: According to an embodiment, a semiconductor device includes a first chip including a substrate, and a second chip bonded to the first chip at a first surface. Each of the first chip and the second chip includes an element region, and an end region including a chip end portion. The first chip includes a plurality of first electrodes that are arranged on the first surface in the end region and are in an electrically uncoupled state. The second chip includes a plurality of second electrodes that are arranged on the first surface in the end region, are in an electrically uncoupled state, and are respectively in contact with the first electrodes.

公开(公告)号：US09887171B2

公开(公告)日：2018-02-06

申请号：US14617530

申请日：2015-02-09

Applicant: SEIKO INSTRUMENTS INC.

Inventor： Makoto Takesawa

IPC: H01L23/495 ,  H01L23/48 ,  H01L23/00 ,  B23K26/53 ,  H01L23/31 ,  B23K103/00

CPC classification number: H01L24/27 ,  B23K26/53 ,  B23K2103/50 ,  B23K2103/56 ,  H01L23/3107 ,  H01L23/3142 ,  H01L24/03 ,  H01L24/08 ,  H01L24/29 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L2224/0801 ,  H01L2224/29339 ,  H01L2224/32013 ,  H01L2224/32145 ,  H01L2224/32245 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48247 ,  H01L2224/4912 ,  H01L2224/49175 ,  H01L2224/73265 ,  H01L2224/92247 ,  H01L2924/10156 ,  H01L2924/12042 ,  H01L2924/181 ,  H01L2924/18301 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/00

Abstract: A semiconductor device has a semiconductor chip adhesively bonded to a die pad. An area having large irregularities is formed on an upper side surface of the semiconductor chip to be covered by an encapsulating resin, and an area having small irregularities is formed on a lower side surface of the semiconductor chip, thereby improving adhesive strength between the semiconductor chip and the encapsulating resin and preventing penetration of moisture from outside.

公开(公告)号：US20170133339A1

公开(公告)日：2017-05-11

申请号：US15410068

申请日：2017-01-19

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： MIRNG-JI LII ,  HAO-YI TSAI ,  HSIEN-WEI CHEN ,  HUNG-YI KUO

IPC: H01L23/00 ,  H01L23/522 ,  H01L23/528 ,  H01L21/66

CPC classification number: H01L24/14 ,  H01L22/14 ,  H01L22/32 ,  H01L23/5226 ,  H01L23/528 ,  H01L24/02 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/08 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/0231 ,  H01L2224/02311 ,  H01L2224/02331 ,  H01L2224/0239 ,  H01L2224/024 ,  H01L2224/034 ,  H01L2224/0347 ,  H01L2224/0361 ,  H01L2224/0392 ,  H01L2224/0401 ,  H01L2224/05018 ,  H01L2224/05073 ,  H01L2224/05166 ,  H01L2224/05551 ,  H01L2224/05552 ,  H01L2224/05556 ,  H01L2224/05569 ,  H01L2224/05572 ,  H01L2224/05611 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2224/05681 ,  H01L2224/05687 ,  H01L2224/061 ,  H01L2224/0612 ,  H01L2224/0801 ,  H01L2224/08059 ,  H01L2224/1146 ,  H01L2224/1147 ,  H01L2224/131 ,  H01L2224/14104 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/81815 ,  H01L2924/15788 ,  H01L2924/00 ,  H01L2924/01029 ,  H01L2924/01013 ,  H01L2924/01028 ,  H01L2924/00014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/00012 ,  H01L2924/014

Abstract: A semiconductor device with an under-bump metallurgy (UBM) over a dielectric is provided. The UBM has a trench configured to be offset from a central point of the UBM. A distance between a center of the trench to an edge of the UBM is larger than a distance between the center of the trench to an opposite edge of the UBM. A probe pin is configured to contact the UBM and collect measurement data.

公开(公告)号：US20150380366A1

公开(公告)日：2015-12-31

申请号：US14517204

申请日：2014-10-17

Applicant: SK hynix Inc.

Inventor： Jae Hong JEONG

IPC: H01L23/00

CPC classification number: H01L24/16 ,  H01L23/522 ,  H01L24/05 ,  H01L24/08 ,  H01L24/13 ,  H01L24/48 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05011 ,  H01L2224/05012 ,  H01L2224/05013 ,  H01L2224/05078 ,  H01L2224/05084 ,  H01L2224/05093 ,  H01L2224/05096 ,  H01L2224/05551 ,  H01L2224/05552 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/05578 ,  H01L2224/0801 ,  H01L2224/08113 ,  H01L2224/08501 ,  H01L2224/08505 ,  H01L2224/13017 ,  H01L2224/13021 ,  H01L2224/13022 ,  H01L2224/13028 ,  H01L2224/16012 ,  H01L2224/16059 ,  H01L2224/16104 ,  H01L2224/48453 ,  H01L2224/48463 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/85399 ,  H01L2224/05599

Abstract: A semiconductor package including a first metal layer configured for use as a bonding pad, a second metal layer formed over the first metal layer, and the second metal layer having a separation allowing for the second metal layer to be positioned above distal ends of the first metal layer. The semiconductor package also including a third metal layer formed over the second metal layer, and the third metal layer having a separation allowing for the third metal layer to be positioned above distal ends of the first metal layer, a trench defined by the separation of the third metal layer and second metal layer, and extending through the third metal layer and the second metal layer to expose the first metal layer, and a bonding ball located within the trench.

Abstract translation: 一种半导体封装，包括被配置为用作焊盘的第一金属层，形成在所述第一金属层上的第二金属层，以及所述第二金属层具有允许所述第二金属层位于所述第一金属层的远端之上的分离 金属层。 所述半导体封装还包括形成在所述第二金属层上的第三金属层，以及所述第三金属层具有允许所述第三金属层位于所述第一金属层的远端之上的分离，所述沟槽由 第三金属层和第二金属层，并且延伸穿过第三金属层和第二金属层以暴露第一金属层，以及位于沟槽内的接合球。

公开(公告)号：US20150187710A1

公开(公告)日：2015-07-02

申请号：US14642531

申请日：2015-03-09

Applicant: DECA Technologies Inc.

Inventor： Christopher M. Scanlan ,  Craig Bishop

IPC: H01L23/00 ,  H01L21/56 ,  H01L21/78 ,  H01L23/31

CPC classification number: H01L24/02 ,  H01L21/56 ,  H01L21/561 ,  H01L21/563 ,  H01L21/568 ,  H01L21/76838 ,  H01L21/78 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/3157 ,  H01L23/48 ,  H01L23/525 ,  H01L23/562 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/08 ,  H01L24/11 ,  H01L24/13 ,  H01L24/19 ,  H01L24/20 ,  H01L24/80 ,  H01L24/92 ,  H01L24/94 ,  H01L24/96 ,  H01L24/97 ,  H01L2224/02311 ,  H01L2224/02313 ,  H01L2224/02331 ,  H01L2224/02371 ,  H01L2224/02372 ,  H01L2224/02377 ,  H01L2224/0239 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/03462 ,  H01L2224/03464 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05008 ,  H01L2224/05024 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05548 ,  H01L2224/05569 ,  H01L2224/05572 ,  H01L2224/05573 ,  H01L2224/0558 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/05666 ,  H01L2224/05669 ,  H01L2224/05671 ,  H01L2224/05687 ,  H01L2224/06187 ,  H01L2224/0801 ,  H01L2224/1132 ,  H01L2224/11334 ,  H01L2224/1145 ,  H01L2224/11452 ,  H01L2224/11462 ,  H01L2224/11464 ,  H01L2224/11849 ,  H01L2224/11901 ,  H01L2224/12105 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/2101 ,  H01L2224/214 ,  H01L2224/215 ,  H01L2224/32225 ,  H01L2224/92 ,  H01L2224/94 ,  H01L2224/95001 ,  H01L2224/96 ,  H01L2224/97 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/18162 ,  H01L2924/3511 ,  H01L2224/20 ,  H01L2224/11 ,  H01L2924/01029 ,  H01L2924/014 ,  H01L2924/01028 ,  H01L2924/0105 ,  H01L23/3164 ,  H01L2224/83 ,  H01L2924/00 ,  H01L2924/01082 ,  H01L2924/01074 ,  H01L2924/01023 ,  H01L2924/01013 ,  H01L2924/01079 ,  H01L2924/01047 ,  H01L2224/0231 ,  H01L2924/00014 ,  H01L2924/04941 ,  H01L21/304 ,  H01L2224/03 ,  H01L2224/19

Abstract: A method of making a semiconductor package can comprise forming a plurality of thick redistribution layer (RDL) traces over active surfaces of a plurality of semiconductor die that are electrically connected to contact pads on the plurality of semiconductor die, singulating the plurality of semiconductor die comprising the plurality of thick RDL traces, mounting the singulated plurality of semiconductor die over a temporary carrier with the active surfaces of the plurality of semiconductor die oriented away from the temporary carrier, disposing encapsulant material over the active surfaces and at least four side surfaces of each of the plurality of semiconductor die, over the plurality of thick RDL traces, and over the temporary carrier, forming a via through the encapsulant material to expose at least one of the plurality of thickened RDL traces with respect to the encapsulant material, removing the temporary carrier, and singulating the plurality of semiconductor die.

Abstract translation: 制造半导体封装的方法可以包括在电连接到多个半导体管芯上的接触焊盘的多个半导体管芯的有效表面上形成多个厚的重分布层（RDL）迹线，将多个半导体管芯分离， 多个粗RDL迹线，将多个半导体裸片的多个半导体裸片安装在临时载体上，其中多个半导体管芯的有源表面远离临时载体，将密封剂材料设置在活性表面和每个半导体芯片的至少四个侧表面上 在多个厚RDL迹线上并且在临时载体上方，通过密封剂材料形成通孔以暴露相对于密封剂材料的多个增厚的RDL迹线中的至少一个，去除临时的 载体和单个多个半导体管芯。