公开(公告)号：US20240292603A1

公开(公告)日：2024-08-29

申请号：US18505462

申请日：2023-11-09

Applicant: Micron Technology, Inc.

Inventor： Russell A. Benson ,  Terrence B. McDaniel ,  Vinay Nair

IPC: H10B12/00 ,  H01L21/762

CPC classification number: H10B12/482 ,  H01L21/76224 ,  H10B12/02 ,  H10B12/485

Abstract: Systems, methods and apparatus are provided for damascene digit lines. For instance, a damascene digit line can be formed by forming a plurality of dummy digit lines on a semiconductor substrate that are separated by a first set of vertical trenches, depositing a sacrificial insulating material in the first set of vertical trenches, forming, and depositing an insulating fill material in, a second set of vertical trenches, forming, and depositing a nitride material in, nitride material deposition spaces; removing at least a portion of the semiconductor substrate to form plurality of cell contact deposition spaces, forming cell contacts in the cell contact deposition spaces, removing the dummy digit lines to form a plurality of vertical openings, removing nitride material to form expanded vertical opening, depositing a digit line insulating material in the expanded vertical openings to form digit line deposition spaces, and forming digit lines.

公开(公告)号：US20240260251A1

公开(公告)日：2024-08-01

申请号：US18419808

申请日：2024-01-23

Applicant: Micron Technology, Inc.

Inventor： Dong Wan Kim ,  Russell A. Benson ,  Byung Yoon Kim

IPC: H10B12/00

CPC classification number: H10B12/053 ,  H10B12/315 ,  H10B12/34

Abstract: A method used in forming memory circuitry comprises forming transistors individually comprising one source/drain region and another source/drain region. A channel region is between the one and the another source/drain regions. A conductive gate is operatively proximate the channel region. The conductive gate comprises part of one of a plurality of conductive-gate lines in a substrate. Lines of conductive material are formed directly above and directly against individual of the one and another source/drain regions. Individual of the lines of the conductive material are between immediately-laterally-adjacent of the conductive-gate lines. The lines of the conductive material directly above the another source/drain regions are etched through to form islands of the conductive material that are individually directly above and directly against the individual one source/drain regions. Storage elements are formed that are individually electrically coupled to individual of the one source/drain regions through individual of the islands of the conductive material. Other embodiments, including structure, are disclosed.

公开(公告)号：US11164876B2

公开(公告)日：2021-11-02

申请号：US16270201

申请日：2019-02-07

Applicant: Micron Technology, Inc.

Inventor： Russell A. Benson

IPC: H01L27/108 ,  H01L21/311 ,  H01L21/02

Abstract: Systems, apparatuses, and methods related to atom implantation for passivation of pillar material are described. An example apparatus includes a pillar of a semiconductor device. The pillar may include a first portion (e.g., a passivation material) formed from silicon nitride and an underlying second portion formed from a conductive material. A region of the first portion opposite from an interface between the first portion and the underlying second portion may be implanted with atoms of an element different from silicon (Si) and nitrogen (N) to enhance passivation of the implanted region.

公开(公告)号：US11342336B1

公开(公告)日：2022-05-24

申请号：US17166342

申请日：2021-02-03

Applicant: Micron Technology, Inc.

Inventor： Russell A. Benson

IPC: H01L27/108

Abstract: A method used in forming integrated circuitry comprises forming horizontally-spaced conductive vias above a substrate. Conducting material is formed directly above and directly against the conductive vias. The conducting material is patterned to form individual conductive lines that are individually directly above a plurality of the conductive vias that are spaced longitudinally-along the respective individual conductive line. The patterning forms the individual conductive lines to have longitudinally-alternating wider and narrower regions. The wider regions are directly above and directly against a top surface of individual of the conductive vias and are wider in a horizontal cross-section that is at the top surface than are the narrower regions in the horizontal cross-section. The narrower regions are longitudinally-between the wider regions. Other embodiments, including structure independent of method, are disclosed.

公开(公告)号：US20220059469A1

公开(公告)日：2022-02-24

申请号：US16999817

申请日：2020-08-21

Applicant: Micron Technology, Inc.

Inventor： Russell A. Benson ,  Davide Colombo ,  Yan Li ,  Terrence B. McDaniel ,  Vinay Nair ,  Silvia Borsari

IPC: H01L23/552 ,  H01L27/108

Abstract: A method of forming a microelectronic device comprises forming a conductive shielding material over a conductive shielding structure and a first dielectric structure horizontally adjacent the conductive shielding structure. A second dielectric structure is formed on first dielectric structure and horizontally adjacent the conductive shielding material. The conductive shielding material and the second dielectric structure are patterned to form fin structures extending in parallel in a first horizontal direction. Each of the fin structures comprises two dielectric end structures integral with remaining portions of the second dielectric structure, and an additional conductive shielding structure interposed between the two dielectric end structures in the first horizontal direction. Conductive lines are formed to extend in parallel in the first horizontal direction and to horizontally alternate with the fin structures in a second horizontal direction orthogonal to the first horizontal direction. Microelectronic devices, memory devices, and electronic systems are also described.

公开(公告)号：US20210005455A1

公开(公告)日：2021-01-07

申请号：US16459079

申请日：2019-07-01

Applicant: Micron Technology, Inc.

Inventor： Yiping Wang ,  Caizhi Xu ,  Pengyuan Zheng ,  Ying Rui ,  Russell A. Benson ,  Yongjun J. Hu ,  Jaydeb Goswami

IPC: H01L21/033 ,  H01L21/308 ,  H01L27/108

Abstract: Systems, apparatuses, and methods related to atom implantation for reduction of compressive stress are described. An example method may include patterning a working surface of a semiconductor, the working surface having a hard mask material formed over a dielectric material and forming a material having a lower refractive index (RI), relative to a RI of the hard mask material, over the hard mask material. The method may further include implanting atoms through the lower RI material and into the hard mask material to reduce the compressive stress in the hard mask material.

公开(公告)号：US11563011B2

公开(公告)日：2023-01-24

申请号：US17038799

申请日：2020-09-30

Applicant: Micron Technology, Inc.

Inventor： Vinay Nair ,  Silvia Borsari ,  Ryan L. Meyer ,  Russell A. Benson ,  Yi Fang Lee

IPC: H01L27/108 ,  G11C5/10 ,  G11C11/402

Abstract: A method used in forming integrated circuitry comprises forming conductive material over a substrate. The conductive material is patterned into a conductive line that is horizontally longitudinally elongated. The conductive material is vertically recessed in longitudinally-spaced first regions of the conductive line to form longitudinally-spaced conductive pillars that individually are in individual longitudinally-spaced second regions that longitudinally-alternate with the longitudinally-spaced first regions along the conductive line. The conductive pillars project vertically relative to the conductive material in the longitudinally-spaced and vertically-recessed first regions of the conductive line. Electronic components are formed directly above the conductive pillars. Individual of the electronic components are directly electrically coupled to individual of the conductive pillars. Additional methods, including structure independent of method, are disclosed.

公开(公告)号：US11257766B1

公开(公告)日：2022-02-22

申请号：US16999817

申请日：2020-08-21

Applicant: Micron Technology, Inc.

Inventor： Russell A. Benson ,  Davide Colombo ,  Yan Li ,  Terrence B. McDaniel ,  Vinay Nair ,  Silvia Borsari

IPC: H01L23/552 ,  H01L27/108

Abstract: A method of forming a microelectronic device comprises forming a conductive shielding material over a conductive shielding structure and a first dielectric structure horizontally adjacent the conductive shielding structure. A second dielectric structure is formed on first dielectric structure and horizontally adjacent the conductive shielding material. The conductive shielding material and the second dielectric structure are patterned to form fin structures extending in parallel in a first horizontal direction. Each of the fin structures comprises two dielectric end structures integral with remaining portions of the second dielectric structure, and an additional conductive shielding structure interposed between the two dielectric end structures in the first horizontal direction. Conductive lines are formed to extend in parallel in the first horizontal direction and to horizontally alternate with the fin structures in a second horizontal direction orthogonal to the first horizontal direction. Microelectronic devices, memory devices, and electronic systems are also described.

公开(公告)号：US20210193460A1

公开(公告)日：2021-06-24

申请号：US16723557

申请日：2019-12-20

Applicant: Micron Technology, Inc.

Inventor： Russell A. Benson ,  Silvia Borsari ,  Vinay Nair ,  Ying Rui ,  Somik Mukherjee

IPC: H01L21/02 ,  H01L21/311 ,  H01L21/3213

Abstract: Methods, apparatuses, and systems related to a semiconductor nitridation passivation are described. An example method includes performing a dry etch process on a semiconductor structure on a wafer in a semiconductor fabrication process. The method further includes performing a dry strip process on the semiconductor structure. The method further includes performing a first wet strip clean process on the semiconductor. The method further includes performing a second wet strip clean process on the semiconductor. The method further includes performing a nitridation passivation on the semiconductor structure to avoid oxidization of the semiconductor structure. The method further performing a spacer material deposition on the semiconductor structure.

公开(公告)号：US10134741B2

公开(公告)日：2018-11-20

申请号：US15652724

申请日：2017-07-18

Applicant: Micron Technology, Inc.

Inventor： Guangjun Yang ,  Russell A. Benson ,  Brent Gilgen ,  Alex J. Schrinsky ,  Sanh D. Tang ,  Si-Woo Lee

IPC: H01L21/768 ,  H01L27/108

Abstract: A method of forming an elevationally extending conductor laterally between a pair of conductive lines comprises forming a pair of conductive lines spaced from one another in at least one vertical cross-section. Conductor material is formed to elevationally extend laterally between and cross elevationally over the pair of conductive lines in the at least one vertical cross-section. Sacrificial material is laterally between the elevationally extending conductor material and each of the conductive lines of the pair in the at least one vertical cross-section. The sacrificial material is removed from between the elevationally extending conductor material and each of the conductive lines of the pair while the conductor material is crossing elevationally over the pair of conductive lines to form a void space laterally between the elevationally extending conductor material and each of the conductive lines of the pair in the at least one vertical cross-section.