公开(公告)号：US11672120B2

公开(公告)日：2023-06-06

申请号：US17328237

申请日：2021-05-24

Applicant: Micron Technology, Inc.

Inventor： Byeung Chui Kim ,  Francois H. Fabreguette ,  Richard J. Hill ,  Purnima Narayanan ,  Shyam Surthi

IPC: H01L27/11582 ,  H01L21/02 ,  H01L27/1157 ,  G11C16/08

CPC classification number: H01L27/11582 ,  G11C16/08 ,  H01L21/0214 ,  H01L27/1157

Abstract: Some embodiments include a memory array having a vertical stack of alternating insulative levels and wordline levels. The wordline levels have conductive terminal ends within control gate regions. The control gate regions are vertically spaced from one another by first insulative regions which include first insulative material. Charge-storage material is laterally outward of the conductive terminal ends, and is configured as segments. The segments of the charge-storage material are arranged one atop another and are vertically spaced from one another by second insulative regions which include second insulative material. The second insulative material has a different dielectric constant than the first insulative material. Charge-tunneling material extends vertically along the stack, and is adjacent to the segments of the charge-trapping material. Channel material extends vertically along the stack, and is adjacent to the charge-tunneling material. Some embodiments include methods of forming integrated assemblies.