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    PRE-DECODER CIRCUITRY
    2.
    发明公开
    PRE-DECODER CIRCUITRY 审中-公开

    公开(公告)号：US20240265965A1

    公开(公告)日：2024-08-08

    申请号：US18639690

    申请日：2024-04-18

    Applicant: Micron Technology, Inc.

    Inventor： Vijayakrishna J. Vankayala ,  Hari Giduturi ,  Jeffrey E. Koelling ,  Mingdong Cui ,  Ramachandra Rao Jogu

    IPC: G11C13/00 ,  H03K19/20

    CPC classification number: G11C13/0023 ,  G11C13/0004 ,  G11C2213/15 ,  H03K19/20

    Abstract: The present disclosure includes apparatuses, methods, and systems for pre-decoder circuitry. An embodiment includes a memory array including a plurality of memory cells, decoder circuitry coupled to the memory array, wherein the decoder circuitry comprises a p-type transistor having a first gate, a first n-type transistor having a second gate, and a second n-type transistor having a third gate, and pre-decoder circuitry configured to provide a bias condition for the first gate, the second gate, and the third gate to provide a selection signal to one of the plurality of memory cells, wherein the bias condition comprises zero volts for the first gate, the second gate, and the third gate for a positive configuration for the memory cells and a negative voltage for the third gate and zero volts for the first gate and the second gate for a negative configuration for the memory cells.

    READ OPERATIONS FOR A MEMORY ARRAY AND REGISTER
    3.
    发明公开
    READ OPERATIONS FOR A MEMORY ARRAY AND REGISTER 审中-公开

    公开(公告)号：US20240242746A1

    公开(公告)日：2024-07-18

    申请号：US18416770

    申请日：2024-01-18

    Applicant: Micron Technology, Inc.

    Inventor： Vijayakrishna J. Vankayala

    IPC: G11C7/10

    CPC classification number: G11C7/1039 ,  G11C7/1012 ,  G11C7/1063 ,  G11C7/1066 ,  G11C7/109 ,  G11C7/1093

    Abstract: Methods, systems, and devices for read operations for a memory array and register are described. In some examples, a memory device may include one or more memory arrays and one or more registers (e.g., one or more mode registers). The memory device may include circuitry that allows for a command to access a memory array and a command to access a register to be received consecutively (e.g., during consecutive sets of clock cycles). Because the commands may be received during consecutive sets of clock cycles, the corresponding data may also be output from the memory array and register during consecutive clock cycles.

    Asymmetric Read-Write Sequence for Interconnected Dies
    5.
    发明公开
    Asymmetric Read-Write Sequence for Interconnected Dies 审中-公开

    公开(公告)号：US20240070093A1

    公开(公告)日：2024-02-29

    申请号：US17823443

    申请日：2022-08-30

    Applicant: Micron Technology, Inc.

    Inventor： Hyun Yoo Lee ,  Kang-Yong Kim ,  Jason McBride Brown ,  Venkatraghavan Bringivijayaraghavan ,  Vijayakrishna J. Vankayala

    IPC: G06F13/16 ,  G06F13/40

    CPC classification number: G06F13/1621 ,  G06F13/1689 ,  G06F13/4068

    Abstract: Apparatuses and techniques for implementing an asymmetric read-write sequence for interconnected dies are described. The asymmetric read-write sequence refers to an asymmetric die-access sequence for read versus write operations. The “asymmetric” term refers to a difference in an order in which data is written to or read from interface and linked dies of the interconnected die architecture. The orders for the read and write operations can be chosen such that a delay associated with transferring data between the interconnected dies occurs as data passes between the interface die and a memory controller. With asymmetric read-write burst sequences, overall timing of the read and write operations of a memory device may be impacted less, if at all, by a timing delay associated with the interconnected die architecture.

    PROCESSING MULTI-CYCLE COMMANDS IN MEMORY DEVICES, AND RELATED METHODS, DEVICES, AND SYSTEMS
    8.
    发明申请
    PROCESSING MULTI-CYCLE COMMANDS IN MEMORY DEVICES, AND RELATED METHODS, DEVICES, AND SYSTEMS 有权

    公开(公告)号：US20210166742A1

    公开(公告)日：2021-06-03

    申请号：US16700212

    申请日：2019-12-02

    Applicant: Micron Technology, Inc.

    Inventor： Vijayakrishna J. Vankayala

    IPC: G11C7/22 ,  G11C7/10 ,  G11C7/06 ,  G11C11/408

    Abstract: Methods of operating a memory device are disclosed. A method may include receiving, at a first die of a number of dies, a first number of bits including one or more command bits, one or more identification bits, and a first number of address bits associated with a command during a first clock cycle. The method may further include conveying, from the first die to at least one other die, at least some of the first number of bits. Further, the method may include receiving, at the first die, a second number of bits including a second number of address bits associated with the command during a second, subsequent clock cycle. Also, the method may include conveying, from the first die to the at least one other die, at least some of the second number of bits. Memory devices and electronic systems are also disclosed.

    Memory device with a clocking mechanism
    9.
    发明授权
    Memory device with a clocking mechanism 有权

    公开(公告)号：US11024349B2

    公开(公告)日：2021-06-01

    申请号：US16401057

    申请日：2019-05-01

    Applicant: Micron Technology, Inc.

    Inventor： Jason M. Brown ,  Vijayakrishna J. Vankayala ,  Todd A. Dauenbaugh

    IPC: G11C7/22

    Abstract: A memory device includes a first data driver configured to send a first data according to a first clock signal; a first data port electrically coupled to the first data driver, the first data port configured to receive the first data; a second data driver configured to send a second data according to a second clock signal, wherein the second clock signal does not match the first clock signal; and a second data port electrically coupled to the second data driver, the second data port configured to receive the second data.

    REDUCED PEAK SELF-REFRESH CURRENT IN A MEMORY DEVICE
    10.
    发明申请
    REDUCED PEAK SELF-REFRESH CURRENT IN A MEMORY DEVICE 审中-公开

    公开(公告)号：US20200219557A1

    公开(公告)日：2020-07-09

    申请号：US16825759

    申请日：2020-03-20

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Vijayakrishna J. Vankayala

    IPC: G11C11/406 ,  G06F1/10 ,  G06F3/06

    Abstract: Devices and methods include organizing memory units of a memory device into a number of groups. The devices and methods also include self-refreshing each group of memory units on different corresponding sequential clock pulses of a self-refresh clock. Specifically, at least one of each group of memory units counts pulses of a self-refresh clock and invokes a self-refresh after every nth pulse of a cycle of pulses while not invoking a self-refresh on all other pulses of the cycle of pulses.

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