公开(公告)号：US20250133719A1

公开(公告)日：2025-04-24

申请号：US18777365

申请日：2024-07-18

Applicant: Micron Technology, Inc.

Inventor： Fatma Arzum Simsek-Ege ,  Christopher K. Morzano ,  Efe Sinan Ege

IPC: H10B12/00

Abstract: A variety of applications can include a memory device having an array of memory cells, with each of the memory cells having a gate-all-around (GAA) transistor arranged as a hexagonal vertical channel transistor coupled to a capacitor. Access lines can be coupled to gates of the GAA transistors and digit lines can be coupled to pillar channels of the GAA transistors. A lattice can be included between the access lines and the digit lines, where the lattice has dielectric regions between and contacting non-dielectric regions. Each non-dielectric region can be positioned on and contacting a digit line and can contain digit contact junctions to the pillar channels of a set of the GAA transistors extending from the non-dielectric region. Additional devices and methods are disclosed.

公开(公告)号：US20240194251A1

公开(公告)日：2024-06-13

申请号：US18499934

申请日：2023-11-01

Applicant: Micron Technology, Inc.

Inventor： Richard E. Fackenthal ,  Christopher K. Morzano ,  Daniele Vimercati

IPC: G11C11/4097

CPC classification number: G11C11/4097

Abstract: Devices and methods for operating a memory device including multiple memory cells configured to store data and multiple global digit lines configured to carry the data in memory accesses of the memory cells. The memory device also includes multiple local digit lines configured to carry the data between the global digit lines and the memory cells. The memory device further includes multiple digit line selection circuits configured to selectively couple selected local digit lines of the local digit lines to the global digit lines. The memory device also includes a controller configured to select a pattern of selected digit line selection circuits to at least partially cancel capacitive coupling between the selected local digit lines.

公开(公告)号：US11967362B2

公开(公告)日：2024-04-23

申请号：US17829737

申请日：2022-06-01

Applicant: Micron Technology, Inc.

Inventor： Huy T. Vo ,  Christopher K. Morzano ,  Christopher J. Kawamura ,  Charles L. Ingalls

IPC: G11C16/04 ,  G11C11/4091

CPC classification number: G11C11/4091

Abstract: A memory device includes multiple memory cells configured to store data. The memory device also includes multiple digit lines each configured to carry data to and from a respective memory cell. The memory device further includes multiple sense amplifiers each selectively coupled to respective digit lines and including first and second NMOS transistors and first and second gut nodes coupled to the first and second NMOS transistors, respectively. Each sense amplifier is configured to perform threshold compensation for the first and second NMOS transistors by storing respective voltages at the first and second gut nodes that are proportional to the respective threshold voltages of the first and second NMOS transistors. The sense amplifier also amplifies a differential voltage between the first and second gut nodes by charging the first gut node and discharging the second gut node based at least in part on respective charges of the digit lines.

公开(公告)号：US20230395130A1

公开(公告)日：2023-12-07

申请号：US17829737

申请日：2022-06-01

Applicant: Micron Technology, Inc.

Inventor： Huy T. Vo ,  Christopher K. Morzano ,  Christopher J. Kawamura ,  Charles L. Ingalls

IPC: G11C11/4091

CPC classification number: G11C11/4091

Abstract: A memory device includes multiple memory cells configured to store data. The memory device also includes multiple digit lines each configured to carry data to and from a respective memory cell. The memory device further includes multiple sense amplifiers each selectively coupled to respective digit lines and including first and second NMOS transistors and first and second gut nodes coupled to the first and second NMOS transistors, respectively. Each sense amplifier is configured to perform threshold compensation for the first and second NMOS transistors by storing respective voltages at the first and second gut nodes that are proportional to the respective threshold voltages of the first and second NMOS transistors. The sense amplifier also amplifies a differential voltage between the first and second gut nodes by charging the first gut node and discharging the second gut node based at least in part on respective charges of the digit lines.

公开(公告)号：US09484326B2

公开(公告)日：2016-11-01

申请号：US14563222

申请日：2014-12-08

Applicant: Micron Technology, Inc.

Inventor： Brent Keeth ,  Christopher K. Morzano

IPC: G06F13/14 ,  H01L25/065 ,  G06F13/38 ,  H01L23/48 ,  H01L25/18 ,  G11C5/02 ,  H01L23/31

CPC classification number: H01L25/0652 ,  G06F13/385 ,  G11C5/02 ,  H01L23/3128 ,  H01L23/481 ,  H01L25/0657 ,  H01L25/18 ,  H01L2224/16145 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06544 ,  H01L2225/06555

Abstract: Various embodiments include apparatuses having stacked devices and methods of forming dice stacks on an interface die. In one such apparatus, a dice stack includes at least a first die and a second die, and conductive paths coupling the first die and the second die to the common control die. In some embodiments, the conductive paths may be arranged to connect with circuitry on alternating dice of the stack. In other embodiments, a plurality of dice stacks may be arranged on a single interface die, and some or all of the dice may have interleaving conductive paths.

Abstract translation: 各种实施例包括具有堆叠装置的装置和在接口管芯上形成管芯叠层的方法。 在一种这样的装置中，骰子堆叠包括至少第一模具和第二模具，以及将第一模具和第二模具耦合到公共控制模具的导电路径。 在一些实施例中，导电路径可以布置成与堆叠的交替管芯上的电路连接。 在其他实施例中，多个骰子堆可以被布置在单个接口管芯上，并且骰子的一些或全部可以具有交错导电路径。

公开(公告)号：US20250048614A1

公开(公告)日：2025-02-06

申请号：US18745962

申请日：2024-06-17

Applicant: Micron Technology, Inc.

Inventor： Fatma Arzum Simsek-Ege ,  David A. Daycock ,  Christopher K. Morzano

IPC: H10B12/00

Abstract: A microelectronic device comprises a first transistor structure comprising multiple vertical levels of channel regions, a second transistor structure neighboring the first transistor structure and comprising additional multiple vertical levels of channel regions, a storage device vertically overlying the first transistor structure and the second transistor structure, a first conductive contact structure contacting the first transistor structure, and a second conductive contact structure contacting the second transistor structure. Related memory devices and electronic systems are also described.

公开(公告)号：US20150091189A1

公开(公告)日：2015-04-02

申请号：US14563222

申请日：2014-12-08

Applicant: Micron Technology, Inc.

Inventor： Brent Keeth ,  Christopher K. Morzano

IPC: H01L25/18 ,  H01L25/065 ,  H01L23/48

CPC classification number: H01L25/0652 ,  G06F13/385 ,  G11C5/02 ,  H01L23/3128 ,  H01L23/481 ,  H01L25/0657 ,  H01L25/18 ,  H01L2224/16145 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06544 ,  H01L2225/06555

Abstract: Various embodiments include apparatuses having stacked devices and methods of forming dice stacks on an interface die. In one such apparatus, a dice stack includes at least a first die and a second die, and conductive paths coupling the first die and the second die to the common control die. In some embodiments, the conductive paths may be arranged to connect with circuitry on alternating dice of the stack. In other embodiments, a plurality of dice stacks may be arranged on a single interface die, and some or all of the dice may have interleaving conductive paths.

Abstract translation: 各种实施例包括具有堆叠装置的装置和在接口管芯上形成管芯堆叠的方法。 在一种这样的装置中，骰子堆叠包括至少第一模具和第二模具，以及将第一模具和第二模具耦合到公共控制模具的导电路径。 在一些实施例中，导电路径可以布置成与堆叠的交替管芯上的电路连接。 在其他实施例中，多个骰子堆可以被布置在单个接口管芯上，并且骰子的一些或全部可以具有交错导电路径。