公开(公告)号：US08930643B2

公开(公告)日：2015-01-06

申请号：US14299237

申请日：2014-06-09

Applicant: Micron Technology, Inc.

Inventor： Dan Skinner ,  J. Thomas Pawlowski

IPC: G06F13/00 ,  G06F13/28 ,  G11C7/10

CPC classification number: G06F13/1631 ,  G06F13/16 ,  G06F13/1636 ,  G11C7/1075 ,  G11C8/16 ,  Y02D10/14

Abstract: Multi-port memory having an additional control bus for passing commands between ports have individual ports that can be configured to respond to a command received from an external control bus or to a command received from the additional control bus. This facilitates various combinations of ports to vary the bandwidth or latency of the memory to facilitate tailoring performance characteristics to differing applications.

Abstract translation: 具有用于在端口之间传递命令的附加控制总线的多端口存储器具有可被配置为响应从外部控制总线接收的命令或从附加控制总线接收的命令的各个端口。 这有助于端口的各种组合来改变存储器的带宽或延迟，以便于针对不同的应用定制性能特征。

公开(公告)号：US09164698B2

公开(公告)日：2015-10-20

申请号：US14269873

申请日：2014-05-05

Applicant: Micron Technology, Inc.

Inventor： Robert M. Walker ,  Dan Skinner ,  J. Thomas Pawlowski

IPC: G06F3/06 ,  G11C7/10 ,  G11C8/12

CPC classification number: G06F3/0659 ,  G06F3/0604 ,  G06F3/0683 ,  G11C7/10 ,  G11C7/1006 ,  G11C8/12

Abstract: Memories having internal processors and methods of data communication within such memories are provided. One such memory may include a fetch unit configured to substantially control performing commands on a memory array based on the availability of banks to be accessed. The fetch unit may receive instructions including commands indicating whether data is to be read from or written to a bank, and the address of the data to be read from or written to the bank. The fetch unit may perform the commands based on the availability of the bank. In one embodiment, control logic communicates with the fetch unit when an activated bank is available. In another implementation, the fetch unit may wait for a bank to become available based on timers set to when a previous command in the activated bank has been performed.

Abstract translation: 提供具有内部处理器的记忆和在这种存储器内的数据通信方法。 一个这样的存储器可以包括提取单元，其被配置为基于要访问的存储体的可用性来基本上控制对存储器阵列执行命令。 取出单元可以接收包括指示数据是从数据读取还是写入银行的指令的指令以及要从银行读取或写入银行的数据的地址。 提取单元可以基于银行的可用性来执行命令。 在一个实施例中，当激活的库可用时，控制逻辑与提取单元进行通信。 在另一实现中，提取单元可以基于当已经执行了激活的存储体中的先前命令时设置的定时器来等待存储体可用。

公开(公告)号：US20140289482A1

公开(公告)日：2014-09-25

申请号：US14299237

申请日：2014-06-09

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Dan Skinner ,  J. Thomas Pawlowski

IPC: G06F13/16 ,  G11C7/10

CPC classification number: G06F13/1631 ,  G06F13/16 ,  G06F13/1636 ,  G11C7/1075 ,  G11C8/16 ,  Y02D10/14

Abstract: Multi-port memory having an additional control bus for passing commands between ports have individual ports that can be configured to respond to a command received from an external control bus or to a command received from the additional control bus. This facilitates various combinations of ports to vary the bandwidth or latency of the memory to facilitate tailoring performance characteristics to differing applications.

Abstract translation: 具有用于在端口之间传递命令的附加控制总线的多端口存储器具有可被配置为响应从外部控制总线接收的命令或从附加控制总线接收的命令的各个端口。 这有助于端口的各种组合来改变存储器的带宽或延迟，以便于针对不同的应用定制性能特征。

公开(公告)号：US20220350760A1

公开(公告)日：2022-11-03

申请号：US17864629

申请日：2022-07-14

Applicant: Micron Technology, Inc.

Inventor： Robert M. Walker ,  Dan Skinner ,  Todd A. Merritt ,  J. Thomas Pawlowski

IPC: G06F13/16 ,  G06F12/0813 ,  G06F15/78 ,  G06F3/06 ,  G06F9/30 ,  G06F13/40

Abstract: Memory having internal processors, and methods of data communication within such a memory are provided. In one embodiment, an internal processor may concurrently access one or more banks on a memory array on a memory device via one or more buffers. The internal processor may be coupled to a buffer capable of accessing more than one bank, or coupled to more than one buffer that may each access a bank, such that data may be retrieved from and stored in different banks concurrently. Further, the memory device may be configured for communication between one or more internal processors through couplings between memory components, such as buffers coupled to each of the internal processors. Therefore, a multi-operation instruction may be performed by different internal processors, and data (such as intermediate results) from one internal processor may be transferred to another internal processor of the memory, enabling parallel execution of an instruction(s).

公开(公告)号：US20170024337A1

公开(公告)日：2017-01-26

申请号：US15288077

申请日：2016-10-07

Applicant: Micron Technology, Inc.

Inventor： Robert M. Walker ,  Dan Skinner ,  Todd A. Merritt ,  J. Thomas Pawlowski

IPC: G06F13/16 ,  G06F13/40 ,  G06F9/30 ,  G06F3/06

CPC classification number: G06F13/1673 ,  G06F3/0613 ,  G06F3/0625 ,  G06F3/0659 ,  G06F3/067 ,  G06F3/0683 ,  G06F9/3001 ,  G06F9/30043 ,  G06F12/0813 ,  G06F13/4068 ,  G06F15/7821

Abstract: Memory having internal processors, and methods of data communication within such a memory are provided. In one embodiment, an internal processor may concurrently access one or more banks on a memory array on a memory device via one or more buffers. The internal processor may be coupled to a buffer capable of accessing more than one bank, or coupled to more than one buffer that may each access a bank, such that data may be retrieved from and stored in different banks concurrently. Further, the memory device may be configured for communication between one or more internal processors through couplings between memory components, such as buffers coupled to each of the internal processors. Therefore, a multi-operation instruction may be performed by different internal processors, and data (such as intermediate results) from one internal processor may be transferred to another internal processor of the memory, enabling parallel execution of an instruction(s).

Abstract translation: 提供具有内部处理器的存储器，以及在这种存储器内的数据通信方法。 在一个实施例中，内部处理器可以经由一个或多个缓冲器同时访问存储器设备上的存储器阵列上的一个或多个存储体。 内部处理器可以耦合到能够访问多于一个存储体的缓冲器，或者耦合到多个缓冲器，每个缓冲器可以访问存储体，从而可以同时从不同的存储体中检索数据并存储在其中。 此外，存储器设备可以被配置为通过存储器组件（诸如耦合到每个内部处理器的缓冲器）之间的耦合来在一个或多个内部处理器之间进行通信。 因此，可以由不同的内部处理器执行多操作指令，并且可以将来自一个内部处理器的数据（例如中间结果）传送到存储器的另一内部处理器，从而能够并行执行指令。

公开(公告)号：US20140244948A1

公开(公告)日：2014-08-28

申请号：US14269873

申请日：2014-05-05

Applicant: Micron Technology, Inc.

Inventor： Robert M. Walker ,  Dan Skinner ,  J. Thomas Pawlowski

IPC: G06F3/06

CPC classification number: G06F3/0659 ,  G06F3/0604 ,  G06F3/0683 ,  G11C7/10 ,  G11C7/1006 ,  G11C8/12

Abstract: Memories having internal processors and methods of data communication within such memories are provided. One such memory may include a fetch unit configured to substantially control performing commands on a memory array based on the availability of banks to be accessed. The fetch unit may receive instructions including commands indicating whether data is to be read from or written to a bank, and the address of the data to be read from or written to the bank. The fetch unit may perform the commands based on the availability of the bank. In one embodiment, control logic communicates with the fetch unit when an activated bank is available. In another implementation, the fetch unit may wait for a bank to become available based on timers set to when a previous command in the activated bank has been performed.

Abstract translation: 提供具有内部处理器的记忆和在这种存储器内的数据通信方法。 一个这样的存储器可以包括提取单元，其被配置为基于要访问的存储体的可用性来基本上控制对存储器阵列执行命令。 取出单元可以接收包括指示数据是从数据读取还是写入银行的指令的指令以及要从银行读取或写入银行的数据的地址。 提取单元可以基于银行的可用性来执行命令。 在一个实施例中，当激活的库可用时，控制逻辑与提取单元进行通信。 在另一实现中，提取单元可以基于当已经执行了激活的存储体中的先前命令时设置的定时器等待存储体可用。