公开(公告)号：US11763906B2

公开(公告)日：2023-09-19

申请号：US16227393

申请日：2018-12-20

Applicant: Micron Technology, Inc.

Inventor： Todd A. Merritt

IPC: G11C16/34 ,  H03L7/099 ,  G11C16/08 ,  G11C16/10 ,  G11C16/32 ,  G11C7/22 ,  G06F3/06 ,  G11C16/26

CPC classification number: G11C16/3495 ,  G06F3/0653 ,  G06F3/0659 ,  G11C7/222 ,  G11C16/08 ,  G11C16/10 ,  G11C16/26 ,  G11C16/32 ,  H03L7/0995

Abstract: Methods, systems, and devices for degradation signaling for a memory device are described. In one example, a method in accordance with the described techniques may include monitoring, at a memory device, an operational characteristic of the memory device. For example, the threshold voltage of one or more transistors within the memory device may be monitored. The memory device may identify a degradation of the memory device based at least in part on the monitored operational characteristic. Based on identifying the degradation, the memory device may signal, to a host device, an indication of the degradation of the memory device.

公开(公告)号：US20150029804A1

公开(公告)日：2015-01-29

申请号：US13949006

申请日：2013-07-23

Applicant: Micron Technology, Inc.

Inventor： Zhong-Yi Xia ,  Vikram K. Bollu ,  Jonathan L. Gossi ,  Howard C. Kirsch ,  Todd A. Merritt

IPC: G11C8/08

CPC classification number: G11C8/08 ,  G11C11/16 ,  G11C11/4085 ,  G11C11/4091 ,  G11C16/26

Abstract: Apparatuses and methods for adjusting deactivation voltages are described herein. An example apparatus may include a voltage control circuit. The voltage control circuit may be configured to receive an address and to adjust a deactivation voltage of an access line associated with a target group of memory cells from a first voltage to a second voltage based, at least in part, on the address. In some examples, the first voltage may be lower than the second voltage.

Abstract translation: 本文描述了用于调节失活电压的装置和方法。 示例性装置可以包括电压控制电路。 电压控制电路可以被配置为至少部分地基于地址来接收地址并且将与目标存储器单元组相关联的接入线路的从第一电压到第二电压的去激活电压调整。 在一些示例中，第一电压可以低于第二电压。

公开(公告)号：US20220350760A1

公开(公告)日：2022-11-03

申请号：US17864629

申请日：2022-07-14

Applicant: Micron Technology, Inc.

Inventor： Robert M. Walker ,  Dan Skinner ,  Todd A. Merritt ,  J. Thomas Pawlowski

IPC: G06F13/16 ,  G06F12/0813 ,  G06F15/78 ,  G06F3/06 ,  G06F9/30 ,  G06F13/40

Abstract: Memory having internal processors, and methods of data communication within such a memory are provided. In one embodiment, an internal processor may concurrently access one or more banks on a memory array on a memory device via one or more buffers. The internal processor may be coupled to a buffer capable of accessing more than one bank, or coupled to more than one buffer that may each access a bank, such that data may be retrieved from and stored in different banks concurrently. Further, the memory device may be configured for communication between one or more internal processors through couplings between memory components, such as buffers coupled to each of the internal processors. Therefore, a multi-operation instruction may be performed by different internal processors, and data (such as intermediate results) from one internal processor may be transferred to another internal processor of the memory, enabling parallel execution of an instruction(s).

公开(公告)号：US20170024337A1

公开(公告)日：2017-01-26

申请号：US15288077

申请日：2016-10-07

Applicant: Micron Technology, Inc.

Inventor： Robert M. Walker ,  Dan Skinner ,  Todd A. Merritt ,  J. Thomas Pawlowski

IPC: G06F13/16 ,  G06F13/40 ,  G06F9/30 ,  G06F3/06

CPC classification number: G06F13/1673 ,  G06F3/0613 ,  G06F3/0625 ,  G06F3/0659 ,  G06F3/067 ,  G06F3/0683 ,  G06F9/3001 ,  G06F9/30043 ,  G06F12/0813 ,  G06F13/4068 ,  G06F15/7821

Abstract: Memory having internal processors, and methods of data communication within such a memory are provided. In one embodiment, an internal processor may concurrently access one or more banks on a memory array on a memory device via one or more buffers. The internal processor may be coupled to a buffer capable of accessing more than one bank, or coupled to more than one buffer that may each access a bank, such that data may be retrieved from and stored in different banks concurrently. Further, the memory device may be configured for communication between one or more internal processors through couplings between memory components, such as buffers coupled to each of the internal processors. Therefore, a multi-operation instruction may be performed by different internal processors, and data (such as intermediate results) from one internal processor may be transferred to another internal processor of the memory, enabling parallel execution of an instruction(s).

Abstract translation: 提供具有内部处理器的存储器，以及在这种存储器内的数据通信方法。 在一个实施例中，内部处理器可以经由一个或多个缓冲器同时访问存储器设备上的存储器阵列上的一个或多个存储体。 内部处理器可以耦合到能够访问多于一个存储体的缓冲器，或者耦合到多个缓冲器，每个缓冲器可以访问存储体，从而可以同时从不同的存储体中检索数据并存储在其中。 此外，存储器设备可以被配置为通过存储器组件（诸如耦合到每个内部处理器的缓冲器）之间的耦合来在一个或多个内部处理器之间进行通信。 因此，可以由不同的内部处理器执行多操作指令，并且可以将来自一个内部处理器的数据（例如中间结果）传送到存储器的另一内部处理器，从而能够并行执行指令。

公开(公告)号：US09082466B2

公开(公告)日：2015-07-14

申请号：US13949006

申请日：2013-07-23

Applicant: Micron Technology, Inc.

Inventor： Zhong-Yi Xia ,  Vikram K. Bollu ,  Jonathan L. Gossi ,  Howard C. Kirsch ,  Todd A. Merritt

IPC: G11C5/14 ,  G11C8/08 ,  G11C16/26 ,  G11C11/16 ,  G11C11/4091

CPC classification number: G11C8/08 ,  G11C11/16 ,  G11C11/4085 ,  G11C11/4091 ,  G11C16/26

Abstract: Apparatuses and methods for adjusting deactivation voltages are described herein. An example apparatus may include a voltage control circuit. The voltage control circuit may be configured to receive an address and to adjust a deactivation voltage of an access line associated with a target group of memory cells from a first voltage to a second voltage based, at least in part, on the address. In some examples, the first voltage may be lower than the second voltage.

Abstract translation: 本文描述了用于调节失活电压的装置和方法。 示例性装置可以包括电压控制电路。 电压控制电路可以被配置为至少部分地基于地址来接收地址并且将与目标存储器单元组相关联的接入线路的从第一电压到第二电压的去激活电压调整。 在一些示例中，第一电压可以低于第二电压。