公开(公告)号：US10395748B2

公开(公告)日：2019-08-27

申请号：US15183654

申请日：2016-06-15

Applicant: Micron Technology, Inc.

Inventor： Tomoyuki Shibata ,  Chikara Kondo ,  Hiroyuki Tanaka

IPC: G11C29/38 ,  G11C29/44 ,  G11C29/00 ,  G11C29/12 ,  G11C29/14 ,  G11C29/36 ,  G11C29/42 ,  G11C29/48 ,  G11C5/02 ,  G11C29/04

Abstract: Apparatuses and methods of sharing error correction memory on an interface chip are described. An example apparatus includes: at least one memory chip having a plurality of first memory cells and an interface chip coupled to the at least one memory chip and having a control circuit and a storage area. The control circuit detects one or more defective memory cells of the first memory cells of the at least one memory chip. The control circuit further stores first defective address information of the one or more defective memory cells of the first memory cells into the storage area. The interface chip responds to the first defective address information and an access request to access the storage area in place of the at least one memory chip when the access request has been provided with respect to the one or more defective memory cells of the first memory cells.

公开(公告)号：US11222708B2

公开(公告)日：2022-01-11

申请号：US16537076

申请日：2019-08-09

Applicant: Micron Technology, Inc.

Inventor： Tomoyuki Shibata ,  Chikara Kondo ,  Hiroyuki Tanaka

IPC: G11C29/38 ,  G11C29/12 ,  G11C29/00 ,  G11C29/14 ,  G11C29/36 ,  G11C29/42 ,  G11C29/44 ,  G11C29/48 ,  G11C5/02 ,  G11C29/04

Abstract: Apparatuses and methods of sharing error correction memory on an interface chip are described. An example apparatus includes: at least one memory chip having a plurality of first memory cells and an interface chip coupled to the at least one memory chip and having a control circuit and a storage area. The control circuit detects one or more defective memory cells of the first memory cells of the at least one memory chip. The control circuit further stores first defective address information of the one or more defective memory cells of the first memory cells into the storage area. The interface chip responds to the first defective address information and an access request to access the storage area in place of the at least one memory chip when the access request has been provided with respect to the one or more defective memory cells of the first memory cells.

公开(公告)号：US20170365356A1

公开(公告)日：2017-12-21

申请号：US15183654

申请日：2016-06-15

Applicant: Micron Technology, Inc.

Inventor： Tomoyuki Shibata ,  Chikara Kondo ,  Hiroyuki Tanaka

IPC: G11C29/38 ,  G11C29/44

CPC classification number: G11C29/38 ,  G11C5/025 ,  G11C29/1201 ,  G11C29/14 ,  G11C29/36 ,  G11C29/42 ,  G11C29/44 ,  G11C29/4401 ,  G11C29/48 ,  G11C29/78 ,  G11C29/846 ,  G11C2029/0407 ,  G11C2029/1208 ,  G11C2029/3602 ,  G11C2029/4402

Abstract: Apparatuses and methods of sharing error correction memory on an interface chip are described. An example apparatus includes: at least one memory chip having a plurality of first memory cells and an interface chip coupled to the at least one memory chip and having a control circuit and a storage area. The control circuit detects one or more defective memory cells of the first memory cells of the at least one memory chip. The control circuit further stores first defective address information of the one or more defective memory cells of the first memory cells into the storage area. The interface chip responds to the first defective address information and an access request to access the storage area in place of the at least one memory chip when the access request has been provided with respect to the one or more defective memory cells of the first memory cells.