公开(公告)号：US20230207488A1

公开(公告)日：2023-06-29

申请号：US17976409

申请日：2022-10-28

Applicant: Micron Technology, Inc.

Inventor： Faxing Che ,  Hong Wan Ng ,  Yeow Chon Ong ,  Wei Yu ,  Ling Pan ,  Lin Bu

IPC: H01L23/00 ,  H01L25/00 ,  H01L25/065 ,  H01L23/498

CPC classification number: H01L23/562 ,  H01L25/50 ,  H01L25/0652 ,  H01L23/49816 ,  H01L23/49838 ,  H01L2924/1438 ,  H01L2924/182 ,  H01L24/48 ,  H01L24/32 ,  H01L2224/48011 ,  H01L2224/48091 ,  H01L2224/48221 ,  H01L24/73 ,  H01L2224/73265 ,  H01L2224/73215 ,  H01L2224/48145 ,  H01L2224/32145 ,  H01L2224/32245

Abstract: A semiconductor package assembly includes a substrate, a die stack including at least a bottom die, an inert top spacer, and at least a first inert base spacer. The inert top and base spacers are exclusive of any circuits. A top surface of the inert top spacer is directly attached to a bottom surface of the bottom die in the die stack. A top surface of the first inert base spacer is directly attached to a bottom surface of the inert top spacer and a bottom surface of the first inert base spacer is directly attached to the substrate. The footprint of the inert base spacer is smaller than the footprint of the inert top spacer. In some embodiments, the footprint of the inert base spacer is positioned entirely within the footprint of the inert top spacer.