公开(公告)号：US12068283B2

公开(公告)日：2024-08-20

申请号：US17502287

申请日：2021-10-15

申请人： Intel Corporation

发明人： Min-Tih Ted Lai ,  Florence R. Pon ,  Yuhong Cai ,  John G. Meyers

IPC分类号： H01L25/065 ,  H01L21/00 ,  H01L23/00 ,  H01L25/00 ,  H01L21/56

CPC分类号： H01L25/0657 ,  H01L24/96 ,  H01L25/50 ,  H01L21/568 ,  H01L2224/04105 ,  H01L2224/32145 ,  H01L2224/46 ,  H01L2224/4801 ,  H01L2224/48011 ,  H01L2224/48091 ,  H01L2224/48147 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/82039 ,  H01L2224/92247 ,  H01L2225/06506 ,  H01L2225/06548 ,  H01L2225/06562 ,  H01L2225/06582 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2224/48091 ,  H01L2924/00014 ,  H01L2224/73265 ,  H01L2224/32145 ,  H01L2224/48227 ,  H01L2924/00

摘要： An electronic assembly includes a plurality of electronic die arranged into shingles, each shingle having a multiple offset stacked die coupled by cascading connections. Each shingle is arranged in a stack of shingles with alternate shingles having die stacked in opposite directions and offset in a zigzag manner to facilitate vertical electrical connections from a top of the electronic assembly to a bottom die of each shingle.

公开(公告)号：US20230395558A1

公开(公告)日：2023-12-07

申请号：US17829601

申请日：2022-06-01

申请人： NANYA TECHNOLOGY CORPORATION

发明人： Wu-Der YANG

IPC分类号： H01L23/00

CPC分类号： H01L24/48 ,  H01L2924/30101 ,  H01L2924/182 ,  H01L24/73 ,  H01L24/32 ,  H01L2224/32225 ,  H01L2224/73265 ,  H01L2224/48091 ,  H01L2224/48011 ,  H01L2224/48229 ,  H01L2224/48992 ,  H01L2224/48997

摘要： A semiconductor device includes a substrate; an electronic component disposed on the substrate; a bonding wire comprising a first terminal connected to the electronic component and a second terminal connected to the substrate; and a supporter disposed between the first terminal and the second terminal of the bonding wire.

公开(公告)号：US20230260952A1

公开(公告)日：2023-08-17

申请号：US18066195

申请日：2022-12-14

申请人： Mitsubishi Electric Corporation

发明人： Hideki YAMAGUCHI

IPC分类号： H01L23/00 ,  H01L25/07 ,  H01L23/495

CPC分类号： H01L24/49 ,  H01L23/49537 ,  H01L23/49575 ,  H01L24/48 ,  H01L24/85 ,  H01L25/072 ,  H01L24/32 ,  H01L24/73 ,  H01L2224/4903 ,  H01L2224/32245 ,  H01L2224/48011 ,  H01L2224/48091 ,  H01L2224/48096 ,  H01L2224/48101 ,  H01L2224/48106 ,  H01L2224/48111 ,  H01L2224/48139 ,  H01L2224/48245 ,  H01L2224/48465 ,  H01L2224/49052 ,  H01L2224/49112 ,  H01L2224/73265 ,  H01L2224/85205 ,  H01L2224/85345 ,  H01L2924/10253 ,  H01L2924/10272 ,  H01L2924/12032 ,  H01L2924/13055 ,  H01L2924/13091

摘要： A semiconductor device capable of securing an insulation distance between a semiconductor element and a wiring. The semiconductor device includes a first semiconductor element, a second semiconductor element, a first wiring, and a second wiring. The first semiconductor element includes a first main surface and a second main surface. An electrode is formed on the first main surface. The second semiconductor element is disposed at a position different from a position of the first semiconductor element in a thickness direction. The first wiring includes an end connected to the electrode. The end includes an upper surface and a cut surface. Diameter of the second wiring is smaller than diameter of the first wiring. The second wiring includes a first end and a second end. The first end is directly connected to the upper surface of the end of the first wiring.

公开(公告)号：US20230207488A1

公开(公告)日：2023-06-29

申请号：US17976409

申请日：2022-10-28

申请人： Micron Technology, Inc.

发明人： Faxing Che ,  Hong Wan Ng ,  Yeow Chon Ong ,  Wei Yu ,  Ling Pan ,  Lin Bu

IPC分类号： H01L23/00 ,  H01L25/00 ,  H01L25/065 ,  H01L23/498

CPC分类号： H01L23/562 ,  H01L25/50 ,  H01L25/0652 ,  H01L23/49816 ,  H01L23/49838 ,  H01L2924/1438 ,  H01L2924/182 ,  H01L24/48 ,  H01L24/32 ,  H01L2224/48011 ,  H01L2224/48091 ,  H01L2224/48221 ,  H01L24/73 ,  H01L2224/73265 ,  H01L2224/73215 ,  H01L2224/48145 ,  H01L2224/32145 ,  H01L2224/32245

摘要： A semiconductor package assembly includes a substrate, a die stack including at least a bottom die, an inert top spacer, and at least a first inert base spacer. The inert top and base spacers are exclusive of any circuits. A top surface of the inert top spacer is directly attached to a bottom surface of the bottom die in the die stack. A top surface of the first inert base spacer is directly attached to a bottom surface of the inert top spacer and a bottom surface of the first inert base spacer is directly attached to the substrate. The footprint of the inert base spacer is smaller than the footprint of the inert top spacer. In some embodiments, the footprint of the inert base spacer is positioned entirely within the footprint of the inert top spacer.

公开(公告)号：US10008441B2

公开(公告)日：2018-06-26

申请号：US15349113

申请日：2016-11-11

申请人： MEDIATEK INC.

发明人： Shiann-Tsong Tsai

IPC分类号： H01L29/49 ,  H01L23/498 ,  H01L23/367 ,  H01L23/31 ,  H01L23/373

CPC分类号： H01L23/49838 ,  H01L23/13 ,  H01L23/3128 ,  H01L23/3157 ,  H01L23/3675 ,  H01L23/3736 ,  H01L23/4334 ,  H01L23/49816 ,  H01L24/29 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48011 ,  H01L2224/48091 ,  H01L2224/49109 ,  H01L2224/73215 ,  H01L2924/00014 ,  H01L2924/15151 ,  H01L2924/15159 ,  H01L2924/15311 ,  H01L2224/4824 ,  H01L2924/00012 ,  H01L2924/0665 ,  H01L2224/45015 ,  H01L2924/207

摘要： A semiconductor package includes a circuit board, a semiconductor chip, a heat spreading layer, an encapsulant layer, a plurality of conductive connections, and a plurality of solder balls. The circuit board includes opposite first and second surfaces and a plurality of through holes. The semiconductor chip is formed over a center portion of the first surface of the circuit board, having an active surface facing the circuit board. The heat spreading layer is formed over the semiconductor chip. The encapsulant layer is formed over the circuit board, covering heat spreading layer, the semiconductor chip, and the circuit board. The plurality of conductive connections respectively passes through the through holes and electrically connecting the semiconductor chip with the circuit board. The plurality of solder balls are formed over the second surface of the circuit board.

公开(公告)号：US09859257B2

公开(公告)日：2018-01-02

申请号：US15358380

申请日：2016-11-22

申请人： Invensas Corporation

发明人： Javier A. Delacruz ,  Belgacem Haba ,  Tu Tam Vu ,  Rajesh Katkar

IPC分类号： H01L23/495 ,  H01L21/00 ,  H01L25/065 ,  H01L25/10 ,  H01L23/31 ,  H01L23/00 ,  H01L23/498

CPC分类号： H01L25/0657 ,  H01L23/3107 ,  H01L23/49541 ,  H01L23/49551 ,  H01L23/49555 ,  H01L23/49575 ,  H01L23/49838 ,  H01L24/29 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/83 ,  H01L24/85 ,  H01L24/97 ,  H01L25/105 ,  H01L2224/2919 ,  H01L2224/29191 ,  H01L2224/32145 ,  H01L2224/32245 ,  H01L2224/33181 ,  H01L2224/48011 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/48471 ,  H01L2224/49051 ,  H01L2224/4909 ,  H01L2224/49113 ,  H01L2224/49173 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2224/8385 ,  H01L2224/85181 ,  H01L2224/85186 ,  H01L2224/97 ,  H01L2225/0651 ,  H01L2225/06555 ,  H01L2225/06562 ,  H01L2225/06582 ,  H01L2924/00014 ,  H01L2924/181 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/45099 ,  H01L2924/00012 ,  H01L2924/0665 ,  H01L2924/07025 ,  H01L2924/06 ,  H01L2224/83 ,  H01L2224/85 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/85399

摘要： Stacked microelectronic packages comprise microelectronic elements each having a contact-bearing front surface and edge surfaces extending away therefrom, and a dielectric encapsulation region contacting an edge surface. The encapsulation defines first and second major surfaces of the package and a remote surface between the major surfaces. Package contacts at the remote surface include a first set of contacts at positions closer to the first major surface than a second set of contacts, which instead are at positions closer to the second major surface. The packages are configured such that major surfaces of each package can be oriented in a nonparallel direction with the major surface of a substrate, the package contacts electrically coupled to corresponding contacts at the substrate surface. The package stacking and orientation can provide increased packing density.

公开(公告)号：US20170373055A1

公开(公告)日：2017-12-28

申请号：US15700679

申请日：2017-09-11

申请人： RENESAS ELECTRONICS CORPORATION

发明人： Masaki SHIRAISHI ,  Tomoaki UNO ,  Nobuyoshi MATSUURA

IPC分类号： H01L27/06 ,  H02M3/155 ,  H01L29/78 ,  H01L29/66 ,  H01L29/49 ,  H01L29/45 ,  H01L29/423 ,  H01L23/00 ,  H01L23/495 ,  H01L23/31 ,  H01L21/8234 ,  H01L21/28 ,  H02M7/00 ,  H01L29/417 ,  H01L29/10 ,  H01L29/872

CPC分类号： H01L27/0629 ,  H01L21/28035 ,  H01L21/823475 ,  H01L23/3107 ,  H01L23/49524 ,  H01L23/49562 ,  H01L23/49575 ,  H01L24/06 ,  H01L24/37 ,  H01L24/40 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L29/1095 ,  H01L29/41741 ,  H01L29/4232 ,  H01L29/4236 ,  H01L29/4238 ,  H01L29/45 ,  H01L29/456 ,  H01L29/4916 ,  H01L29/66143 ,  H01L29/66734 ,  H01L29/7806 ,  H01L29/7813 ,  H01L29/872 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/05624 ,  H01L2224/371 ,  H01L2224/37124 ,  H01L2224/37147 ,  H01L2224/40095 ,  H01L2224/40245 ,  H01L2224/40247 ,  H01L2224/45015 ,  H01L2224/45144 ,  H01L2224/48011 ,  H01L2224/48091 ,  H01L2224/48095 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/48253 ,  H01L2224/48624 ,  H01L2224/4903 ,  H01L2224/49051 ,  H01L2224/49111 ,  H01L2224/49171 ,  H01L2224/49175 ,  H01L2224/73221 ,  H01L2224/8385 ,  H01L2224/84801 ,  H01L2224/8485 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/01002 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01021 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01057 ,  H01L2924/01072 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12032 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1532 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/20753 ,  H01L2924/20755 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/3011 ,  H02M3/155 ,  H02M7/003

摘要： In a non-insulated DC-DC converter having a circuit in which a power MOS•FET high-side switch and a power MOS•FET low-side switch are connected in series, the power MOS•FET low-side switch and a Schottky barrier diode to be connected in parallel with the power MOS•FET low-side switch are formed within one semiconductor chip. The formation region SDR of the Schottky barrier diode is disposed in the center in the shorter direction of the semiconductor chip, and on both sides thereof, the formation regions of the power MOS•FET low-side switch are disposed. From the gate finger in the vicinity of both long sides on the main surface of the semiconductor chip toward the formation region SDR of the Schottky barrier diode, a plurality of gate fingers are disposed so as to interpose the formation region SDR between them.

公开(公告)号：US09793265B2

公开(公告)日：2017-10-17

申请号：US15265940

申请日：2016-09-15

申请人： RENESAS ELECTRONICS CORPORATION

发明人： Masaki Shiraishi ,  Tomoaki Uno ,  Nobuyoshi Matsuura

IPC分类号： H01L27/06 ,  H01L23/31 ,  H01L23/495 ,  H01L23/00 ,  H01L29/78 ,  H02M7/00 ,  H01L21/28 ,  H01L21/8234 ,  H01L29/49 ,  H01L29/66 ,  H02M3/155 ,  H01L29/10 ,  H01L29/417 ,  H01L29/423 ,  H01L29/45 ,  H01L29/872

CPC分类号： H01L27/0629 ,  H01L21/28035 ,  H01L21/823475 ,  H01L23/3107 ,  H01L23/49524 ,  H01L23/49562 ,  H01L23/49575 ,  H01L24/06 ,  H01L24/37 ,  H01L24/40 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L29/1095 ,  H01L29/41741 ,  H01L29/4232 ,  H01L29/4236 ,  H01L29/4238 ,  H01L29/45 ,  H01L29/456 ,  H01L29/4916 ,  H01L29/66143 ,  H01L29/66734 ,  H01L29/7806 ,  H01L29/7813 ,  H01L29/872 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/05624 ,  H01L2224/371 ,  H01L2224/37124 ,  H01L2224/37147 ,  H01L2224/40095 ,  H01L2224/40245 ,  H01L2224/40247 ,  H01L2224/45015 ,  H01L2224/45144 ,  H01L2224/48011 ,  H01L2224/48091 ,  H01L2224/48095 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/48253 ,  H01L2224/48624 ,  H01L2224/4903 ,  H01L2224/49051 ,  H01L2224/49111 ,  H01L2224/49171 ,  H01L2224/49175 ,  H01L2224/73221 ,  H01L2224/8385 ,  H01L2224/84801 ,  H01L2224/8485 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/01002 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01021 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01057 ,  H01L2924/01072 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12032 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1532 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/20753 ,  H01L2924/20755 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/3011 ,  H02M3/155 ,  H02M7/003

摘要： In a non-insulated DC-DC converter having a circuit in which a power MOS•FET high-side switch and a power MOS•FET low-side switch are connected in series, the power MOS•FET low-side switch and a Schottky barrier diode to be connected in parallel with the power MOS•FET low-side switch are formed within one semiconductor chip. The formation region SDR of the Schottky barrier diode is disposed in the center in the shorter direction of the semiconductor chip, and on both sides thereof, the formation regions of the power MOS•FET low-side switch are disposed. From the gate finger in the vicinity of both long sides on the main surface of the semiconductor chip toward the formation region SDR of the Schottky barrier diode, a plurality of gate fingers are disposed so as to interpose the formation region SDR between them.

公开(公告)号：US20170117244A1

公开(公告)日：2017-04-27

申请号：US15107423

申请日：2015-09-18

申请人： NIPPON MICROMETAL CORPORATION ,  NIPPON STEEL & SUMIKIN MATERIALS CO., LTD.

发明人： Takashi YAMADA ,  Daizo ODA ,  Teruo HAIBARA ,  Tomohiro UNO

IPC分类号： H01L23/00

CPC分类号： H01L24/45 ,  H01L2224/05624 ,  H01L2224/45015 ,  H01L2224/45147 ,  H01L2224/45565 ,  H01L2224/45572 ,  H01L2224/45609 ,  H01L2224/45618 ,  H01L2224/45644 ,  H01L2224/45647 ,  H01L2224/45655 ,  H01L2224/45664 ,  H01L2224/45669 ,  H01L2224/45673 ,  H01L2224/45678 ,  H01L2224/48011 ,  H01L2224/48247 ,  H01L2224/48507 ,  H01L2224/85065 ,  H01L2224/85075 ,  H01L2224/85439 ,  H01L2924/10253 ,  H01L2924/1576 ,  H01L2924/20752 ,  H01L2924/013 ,  H01L2924/01014 ,  H01L2924/01029 ,  H01L2924/01007 ,  H01L2924/01001 ,  H01L2924/01028 ,  H01L2924/00013 ,  H01L2924/20656 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01005 ,  H01L2924/01012 ,  H01L2924/01015 ,  H01L2924/0102 ,  H01L2924/0103 ,  H01L2924/01031 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01034 ,  H01L2924/01045 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/01052 ,  H01L2924/01057 ,  H01L2924/01077 ,  H01L2924/01083 ,  H01L2924/01202 ,  H01L2924/01203 ,  H01L2924/01204

摘要： A bonding wire for a semiconductor device includes a Cu alloy core material and a Pd coating layer formed on a surface thereof, and the boding wire contains one or more elements of As, Te, Sn, Sb, Bi and Se in a total amount of 0.1 to 100 ppm by mass. The bonding longevity of a ball bonded part can increase in a high-temperature and high-humidity environment, improving the bonding reliability. When the Cu alloy core material further contains one or more of Ni, Zn, Rh, In, Ir, Pt, Ga and Ge in an amount, for each, of 0.011 to 1.2% by mass, it is able to increase the reliability of a ball bonded part in a high-temperature environment of 170° C. or more. When an alloy skin layer containing Au and Pd is further formed on a surface of the Pd coating layer, wedge bondability improves.

公开(公告)号：US20170040890A1

公开(公告)日：2017-02-09

申请号：US15295599

申请日：2016-10-17

申请人： Cree, Inc.

发明人： Adam Barkley ,  Marcelo Schupbach

IPC分类号： H02M3/155 ,  H02M7/00 ,  H05K1/03 ,  H05K1/18 ,  H01L23/373 ,  H01L29/16 ,  H01L29/78 ,  H01L29/872 ,  H01L25/18 ,  H01L23/00 ,  H02M1/08 ,  H05K5/02

CPC分类号： H02M3/155 ,  B60L2210/00 ,  C04B37/026 ,  C04B2237/366 ,  C04B2237/368 ,  H01L23/15 ,  H01L23/3735 ,  H01L24/48 ,  H01L24/49 ,  H01L25/072 ,  H01L25/18 ,  H01L29/1608 ,  H01L2224/0603 ,  H01L2224/45015 ,  H01L2224/48011 ,  H01L2224/48091 ,  H01L2224/48157 ,  H01L2224/4903 ,  H01L2224/49111 ,  H01L2224/49431 ,  H01L2924/00014 ,  H01L2924/10272 ,  H01L2924/12032 ,  H01L2924/13091 ,  H01L2924/19105 ,  H02M1/08 ,  H02M1/44 ,  H02M7/003 ,  H02M2001/0054 ,  H02M2001/348 ,  H05K5/0256 ,  Y02B70/1483 ,  H01L2224/05599 ,  H01L2224/45099 ,  H01L2924/20751 ,  H01L2924/2075 ,  H01L2224/85399

摘要： A power converter module includes a baseplate, a substrate on the baseplate, one or more silicon carbide switching components on the substrate, and a housing over the baseplate, the substrate, and the one or more silicon carbide switching components. The housing has a footprint less than 25 cm2. Including a baseplate in a power converter module with a footprint less than 25 cm2 runs counter to accepted design principles for silicon and silicon carbide-based power converter modules, but may improve performance of the power converter module and/or decrease the cost of the power converter module.

摘要翻译： 功率转换器模块包括基板，基板上的基板，基板上的一个或多个碳化硅切换部件，以及在基板，基板和一个或多个碳化硅切换部件上的壳体。 外壳的占地面积小于25平方厘米。 在基于硅和碳化硅的功率转换器模块的接受设计原理中，包括占地面积小于25 cm2的功率转换器模块中的底板与设计原理相反，但可以提高功率转换器模块的性能和/或降低功率成本 转换器模块。