公开(公告)号：US20230207488A1

公开(公告)日：2023-06-29

申请号：US17976409

申请日：2022-10-28

Applicant: Micron Technology, Inc.

Inventor： Faxing Che ,  Hong Wan Ng ,  Yeow Chon Ong ,  Wei Yu ,  Ling Pan ,  Lin Bu

IPC: H01L23/00 ,  H01L25/00 ,  H01L25/065 ,  H01L23/498

CPC classification number: H01L23/562 ,  H01L25/50 ,  H01L25/0652 ,  H01L23/49816 ,  H01L23/49838 ,  H01L2924/1438 ,  H01L2924/182 ,  H01L24/48 ,  H01L24/32 ,  H01L2224/48011 ,  H01L2224/48091 ,  H01L2224/48221 ,  H01L24/73 ,  H01L2224/73265 ,  H01L2224/73215 ,  H01L2224/48145 ,  H01L2224/32145 ,  H01L2224/32245

Abstract: A semiconductor package assembly includes a substrate, a die stack including at least a bottom die, an inert top spacer, and at least a first inert base spacer. The inert top and base spacers are exclusive of any circuits. A top surface of the inert top spacer is directly attached to a bottom surface of the bottom die in the die stack. A top surface of the first inert base spacer is directly attached to a bottom surface of the inert top spacer and a bottom surface of the first inert base spacer is directly attached to the substrate. The footprint of the inert base spacer is smaller than the footprint of the inert top spacer. In some embodiments, the footprint of the inert base spacer is positioned entirely within the footprint of the inert top spacer.

公开(公告)号：US20240038704A1

公开(公告)日：2024-02-01

申请号：US17874206

申请日：2022-07-26

Applicant: Micron Technology, Inc.

Inventor： Faxing Che ,  Hong Wan Ng ,  Yeow Chon Ong

IPC: H01L23/00

CPC classification number: H01L24/13 ,  H01L24/16 ,  H01L24/11 ,  H01L24/81 ,  H01L2224/81815 ,  H01L2224/81203 ,  H01L2924/37001 ,  H01L2924/3512 ,  H01L2224/16148 ,  H01L2224/16221 ,  H01L2224/11462 ,  H01L2224/13007 ,  H01L2224/13014 ,  H01L2224/13017 ,  H01L2224/13019 ,  H01L2224/13076 ,  H01L2224/13147 ,  H01L2224/13541 ,  H01L2224/1355 ,  H01L2224/13655 ,  H01L2224/1369 ,  H01L2224/13582

Abstract: In some embodiments, a semiconductor device assembly can include a first semiconductor die, a second semiconductor die, and an interconnection structure therebetween. The interconnection structure can directly electrically couple the first and the second semiconductor dies. The interconnection structure can include an inner metallic pillar, an outer metallic shell, a continuous metallic bridging layer, and a dielectric liner. The outer metallic shell can surround and be spaced from the inner metallic pillar, the continuous metallic bridging layer can be over and connected with the inner metallic pillar and the outer metallic shell, and the dielectric liner can be between the inner metallic pillar and the outer metallic shell. In some embodiments, the second semiconductor die can be excluded and the interconnection structure can solely be coupled to the first semiconductor die.

公开(公告)号：US20240292522A1

公开(公告)日：2024-08-29

申请号：US18424681

申请日：2024-01-26

Applicant: Micron Technology, Inc.

Inventor： Prasad Nagavenkata Nune ,  Christopher Glancey ,  Yeow Chon Ong ,  Hong Wan Ng

IPC: H05K1/02

CPC classification number: H05K1/0271 ,  H05K2201/09418 ,  H05K2201/10159

Abstract: A microelectronic device package assembly includes a package board and a stiffener device attached to the package board. The package board has a first side and a second side. The stiffener device includes an upper stiffener, a lower stiffener, and one or more damper device. The upper stiffener is above the first side of the package board and has a die side and a package side. The lower stiffener is interposed between the upper stiffener and the package board and has a damper side and a board side. The lower stiffener includes through-package anchors extending from the board side and through the package board. The one or more damper devices are interposed between and are in contact with each of the upper stiffener and the lower stiffener. Microelectronic devices and electronic systems are also described.

公开(公告)号：US20240047285A1

公开(公告)日：2024-02-08

申请号：US17883153

申请日：2022-08-08

Applicant: Micron Technology, Inc.

Inventor： Faxing Che ,  Wei Yu ,  Yeow Chon Ong ,  Shin Yueh Yang ,  Hong Wan Ng

IPC: H01L23/14 ,  H01L21/52

CPC classification number: H01L23/14 ,  H01L21/52

Abstract: A semiconductor device assembly includes a semiconductor die, a substrate, and a spacer directly coupled to the substrate. The spacer includes a flexible main body and a support structure embedded in the flexible main body, wherein the support structure has a higher stiffness than the flexible main body. The spacer carries the semiconductor die. The flexible main body of the spacer mitigates the effects of thermomechanical stress, for example caused by a mismatch between the coefficient of thermal expansion of the semiconductor die and the substrate. The embedded support structure provides strength needed to support the semiconductor die during assembly.

公开(公告)号：US12080616B2

公开(公告)日：2024-09-03

申请号：US17552217

申请日：2021-12-15

Applicant: Micron Technology, Inc.

Inventor： Suresh K. Upadhyayula ,  Yeow Chon Ong ,  Hong Wan Ng

IPC: H01L23/31 ,  H01L21/56 ,  H01L23/00 ,  H01L23/29 ,  H01L25/065

CPC classification number: H01L23/3135 ,  H01L21/56 ,  H01L23/295 ,  H01L23/562 ,  H01L25/0657 ,  H01L23/3121 ,  H01L2225/0651 ,  H01L2225/06562

Abstract: The subject application relates to reinforced semiconductor device packaging and associated systems and methods. The device generally includes a substrate and one or more integrated circuit dies electrically coupled to the substrate with wire bonds. The device includes an encapsulant enclosing the one or more dies and the wire bonds. The package can include a reinforcing layer positioned on one or more surfaces of the encapsulant, a reinforcing wire extending through the encapsulant, or entrained reinforcing fiber portions positioned throughout the encapsulant. The reinforcing layer can be textile woven from synthetic or natural fibers, such as aramid, carbon, or glass. The package can be formed by disposing a reinforcing textile layer in a mold, placing a die and substrate in the mold with a liquid encapsulant, and hardening the liquid encapsulant to adhere the reinforcing textile layer, the encapsulant, the die, and the substrate together.

公开(公告)号：US20240063141A1

公开(公告)日：2024-02-22

申请号：US17891535

申请日：2022-08-19

Applicant: Micron Technology, Inc.

Inventor： Faxing Che ,  Yeow Chon Ong

IPC: H01L23/00 ,  H01L23/498

CPC classification number: H01L23/562 ,  H01L23/49811 ,  H01L23/49838

Abstract: A semiconductor package can include a substrate having bonded thereto an array of solder joints. Each of the solder joints in the array can have a first surface area and a first shape. The semiconductor package can further include at least one differently-sized solder joint having a second surface area larger than the first surface area. The differently-sized solder joint can have a second shape different from the first shape. Other systems, methods and apparatuses are described.

公开(公告)号：US20220208632A1

公开(公告)日：2022-06-30

申请号：US17552217

申请日：2021-12-15

Applicant: Micron Technology, Inc.

Inventor： Suresh K. Upadhyayula ,  Yeow Chon Ong ,  Hong Wan Ng

IPC: H01L23/31 ,  H01L23/29 ,  H01L23/00 ,  H01L25/065 ,  H01L21/56

Abstract: Systems and methods for a semiconductor device having reinforced packaging are provided. The device generally includes a substrate and one or more integrated circuit dies electrically coupled to the substrate with wire bonds. The device includes an encapsulant enclosing the one or more dies and the wire bonds. The package can include a reinforcing layer positioned on one or more surfaces of the encapsulant, a reinforcing wire extending through the encapsulant, or entrained reinforcing fiber portions positioned throughout the encapsulant. The reinforcing layer can be textile woven from synthetic or natural fibers, such as aramid, carbon, or glass. The package can be formed by disposing a reinforcing textile layer in a mold, placing a die and substrate in the mold with a liquid encapsulant, and hardening the liquid encapsulant to adhere the reinforcing textile layer, the encapsulant, the die, and the substrate together.