公开(公告)号：US20200176047A1

公开(公告)日：2020-06-04

申请号：US16205980

申请日：2018-11-30

Applicant: Micron Technology, Inc.

Inventor： Nathaniel J. Meier ,  James S. Rehmeyer ,  Sang-Kyun Park ,  Makoto Kitayama

IPC: G11C11/406 ,  G06F3/06 ,  G11C11/22

Abstract: Methods, systems, and devices for refresh command management are described. A memory device may conduct a refresh operation to preserve the integrity of data stored to one or more memory cells. In some examples, the frequency of refresh operations conducted may be based on the memory device's temperature and may be initiated based on one or more commands received from an external device (e.g., a host device). Each command may be transmitted by the host device at a defined rate, which may impact the rate at which the memory device conducts one or more refresh operations. The memory device may postpone or skip at least a portion of one or more refresh operations based on one or more operating parameters of the memory device.

公开(公告)号：US20210343323A1

公开(公告)日：2021-11-04

申请号：US17319820

申请日：2021-05-13

Applicant: Micron Technology, Inc.

Inventor： Nathaniel J. Meier ,  James S. Rehmeyer ,  Sang-Kyun Park ,  Makoto Kitayama

IPC: G11C11/406 ,  G11C11/22 ,  G06F3/06

Abstract: Methods, systems, and devices for refresh command management are described. A memory device may conduct a refresh operation to preserve the integrity of data stored to one or more memory cells. In some examples, the frequency of refresh operations conducted may be based on the memory device's temperature and may be initiated based on one or more commands received from an external device (e.g., a host device). Each command may be transmitted by the host device at a defined rate, which may impact the rate at which the memory device conducts one or more refresh operations. The memory device may postpone or skip at least a portion of one or more refresh operations based on one or more operating parameters of the memory device.

公开(公告)号：US11017834B2

公开(公告)日：2021-05-25

申请号：US16205980

申请日：2018-11-30

Applicant: Micron Technology, Inc.

Inventor： Nathaniel J. Meier ,  James S. Rehmeyer ,  Sang-Kyun Park ,  Makoto Kitayama

IPC: G11C11/406 ,  G06F3/06 ,  G11C11/22

Abstract: Methods, systems, and devices for refresh command management are described. A memory device may conduct a refresh operation to preserve the integrity of data stored to one or more memory cells. In some examples, the frequency of refresh operations conducted may be based on the memory device's temperature and may be initiated based on one or more commands received from an external device (e.g., a host device). Each command may be transmitted by the host device at a defined rate, which may impact the rate at which the memory device conducts one or more refresh operations. The memory device may postpone or skip at least a portion of one or more refresh operations based on one or more operating parameters of the memory device.

公开(公告)号：US20190304516A1

公开(公告)日：2019-10-03

申请号：US15938965

申请日：2018-03-28

Applicant: Micron Technology, Inc.

Inventor： Hideo Shimizu ,  Makoto Kitayama ,  Mototsugu Fujimitsu

IPC: G11C7/10 ,  G06F11/10 ,  G11C29/52 ,  G11C7/06 ,  G11C8/10 ,  G11C29/42 ,  G11C5/06

Abstract: Apparatuses and methods for coupling data lines in a memory device are disclosed. An example apparatus includes first and second local IO lines, first and second global IO lines, and a control circuit. The control circuit is configured in a write operation to bring the first local IO line and the first global IO line to one of first and second combinations in logic level and the second local IO line and the second global IO line to the other of the first and second combinations in logic level, and further configured in a read operation to cause the first local IO line and the first global IO line into to one of third and fourth combinations in logic level and the second local IO line and the second global IO line to the other of the third and fourth combinations in logic level.