公开(公告)号：US12182432B2

公开(公告)日：2024-12-31

申请号：US17493988

申请日：2021-10-05

Applicant: Micron Technology, Inc.

Inventor： Andrea Martinelli ,  Christophe Vincent Antoine Laurent ,  Claudio Nava ,  Marco Defendi

IPC: G11C11/22 ,  G06F3/06 ,  G06F11/10 ,  G11C11/408 ,  G11C11/4091 ,  G11C29/52

Abstract: Methods, systems, and devices for circuit partitioning for a memory device are described. In one example, a memory device may include a set of memory tiles that each include a respective array of memory cells (e.g., in an array level or layer). Each of the memory tiles may include a respective circuit level or layer associated with circuitry configured to operate the respective array of memory cells. The memory device may also include circuitry for communicating data between the memory cells of the set of memory tiles and an input/output component. Aspects of the circuitry for communicating the data may be subdivided into repeatable blocks each configured to communicate one or more bits, and the repeatable blocks and other aspects of the circuitry for communicating the data is distributed across the circuit layer of two or more of the set of memory tiles.

公开(公告)号：US20220100404A1

公开(公告)日：2022-03-31

申请号：US17493988

申请日：2021-10-05

Applicant: Micron Technology, Inc.

Inventor： Andrea Martinelli ,  Christopher Vincent Antoine Laurent ,  Claudio Nava ,  Marco Defendi

IPC: G06F3/06 ,  G11C11/22 ,  G11C29/52 ,  G11C11/4091 ,  G06F11/10 ,  G11C11/408

Abstract: Methods, systems, and devices for circuit partitioning for a memory device are described. In one example, a memory device may include a set of memory tiles that each include a respective array of memory cells (e.g., in an array level or layer). Each of the memory tiles may include a respective circuit level or layer associated with circuitry configured to operate the respective array of memory cells. The memory device may also include circuitry for communicating data between the memory cells of the set of memory tiles and an input/output component. Aspects of the circuitry for communicating the data may be subdivided into repeatable blocks each configured to communicate one or more bits, and the repeatable blocks and other aspects of the circuitry for communicating the data is distributed across the circuit layer of two or more of the set of memory tiles.

公开(公告)号：US20210011645A1

公开(公告)日：2021-01-14

申请号：US16508729

申请日：2019-07-11

Applicant: Micron Technology, Inc.

Inventor： Andrea Martinelli ,  Christophe Vincent Antoine Laurent ,  Claudio Nava ,  Marco Defendi

IPC: G06F3/06 ,  G11C11/22 ,  G11C11/408 ,  G11C11/4091 ,  G06F11/10 ,  G11C29/52

Abstract: Methods, systems, and devices for circuit partitioning for a memory device are described. In one example, a memory device may include a set of memory tiles that each include a respective array of memory cells (e.g., in an array level or layer). Each of the memory tiles may include a respective circuit level or layer associated with circuitry configured to operate the respective array of memory cells. The memory device may also include circuitry for communicating data between the memory cells of the set of memory tiles and an input/output component. Aspects of the circuitry for communicating the data may be subdivided into repeatable blocks each configured to communicate one or more bits, and the repeatable blocks and other aspects of the circuitry for communicating the data is distributed across the circuit layer of two or more of the set of memory tiles.

公开(公告)号：US11144228B2

公开(公告)日：2021-10-12

申请号：US16508729

申请日：2019-07-11

Applicant: Micron Technology, Inc.

Inventor： Andrea Martinelli ,  Christophe Vincent Antoine Laurent ,  Claudio Nava ,  Marco Defendi

IPC: G06F3/06 ,  G11C11/22 ,  G11C29/52 ,  G11C11/4091 ,  G06F11/10 ,  G11C11/408

Abstract: Methods, systems, and devices for circuit partitioning for a memory device are described. In one example, a memory device may include a set of memory tiles that each include a respective array of memory cells (e.g., in an array level or layer). Each of the memory tiles may include a respective circuit level or layer associated with circuitry configured to operate the respective array of memory cells. The memory device may also include circuitry for communicating data between the memory cells of the set of memory tiles and an input/output component. Aspects of the circuitry for communicating the data may be subdivided into repeatable blocks each configured to communicate one or more bits, and the repeatable blocks and other aspects of the circuitry for communicating the data is distributed across the circuit layer of two or more of the set of memory tiles.