公开(公告)号：US20220122643A1

公开(公告)日：2022-04-21

申请号：US17499303

申请日：2021-10-12

Applicant: Micron Technology, Inc.

Inventor： Christopher Vincent Antoine Laurent ,  Andrea Martinelli

IPC: G11C7/08 ,  G06F13/16 ,  G11C7/10 ,  G11C8/08 ,  G06F3/06 ,  G11C7/12 ,  G11C5/14 ,  G11C8/10

Abstract: Methods, systems, and devices for input/output line sharing for memory subarrays are described. I/O lines may be shared across subarrays, which may correspond to separate memory tiles. The sharing of I/O lines may allow an I/O line to carry data from one subarray in response to access commands associated with one address range, and to carry data from another subarray in response to access commands associated with another address range. In some cases, sense amplifiers and other components may also be shared across subarrays, including across subarrays in different banks. The sharing of I/O lines may, in some cases, support activating only a subset of subarrays in a bank when accessing data stored in the bank, which may provide power savings.

公开(公告)号：US20220100404A1

公开(公告)日：2022-03-31

申请号：US17493988

申请日：2021-10-05

Applicant: Micron Technology, Inc.

Inventor： Andrea Martinelli ,  Christopher Vincent Antoine Laurent ,  Claudio Nava ,  Marco Defendi

IPC: G06F3/06 ,  G11C11/22 ,  G11C29/52 ,  G11C11/4091 ,  G06F11/10 ,  G11C11/408

Abstract: Methods, systems, and devices for circuit partitioning for a memory device are described. In one example, a memory device may include a set of memory tiles that each include a respective array of memory cells (e.g., in an array level or layer). Each of the memory tiles may include a respective circuit level or layer associated with circuitry configured to operate the respective array of memory cells. The memory device may also include circuitry for communicating data between the memory cells of the set of memory tiles and an input/output component. Aspects of the circuitry for communicating the data may be subdivided into repeatable blocks each configured to communicate one or more bits, and the repeatable blocks and other aspects of the circuitry for communicating the data is distributed across the circuit layer of two or more of the set of memory tiles.

公开(公告)号：US11830570B2

公开(公告)日：2023-11-28

申请号：US17499303

申请日：2021-10-12

Applicant: Micron Technology, Inc.

Inventor： Christopher Vincent Antoine Laurent ,  Andrea Martinelli

IPC: G06F3/00 ,  G11C7/08 ,  G06F13/16 ,  G06F3/06 ,  G11C7/10 ,  G11C8/10 ,  G11C5/14 ,  G11C7/12 ,  G11C8/08

CPC classification number: G11C7/08 ,  G06F3/0659 ,  G06F3/0688 ,  G06F13/1657 ,  G06F13/1663 ,  G06F13/1694 ,  G11C5/147 ,  G11C7/109 ,  G11C7/1063 ,  G11C7/1069 ,  G11C7/1096 ,  G11C7/12 ,  G11C8/08 ,  G11C8/10

Abstract: Methods, systems, and devices for input/output line sharing for memory subarrays are described. I/O lines may be shared across subarrays, which may correspond to separate memory tiles. The sharing of I/O lines may allow an I/O line to carry data from one subarray in response to access commands associated with one address range, and to carry data from another subarray in response to access commands associated with another address range. In some cases, sense amplifiers and other components may also be shared across subarrays, including across subarrays in different banks. The sharing of I/O lines may, in some cases, support activating only a subset of subarrays in a bank when accessing data stored in the bank, which may provide power savings.

公开(公告)号：US20210012817A1

公开(公告)日：2021-01-14

申请号：US16508753

申请日：2019-07-11

Applicant: Micron Technology, Inc.

Inventor： Christopher Vincent Antoine Laurent ,  Andrea Martinelli

IPC: G11C7/08 ,  G06F13/16 ,  G06F3/06 ,  G11C8/08 ,  G11C8/10 ,  G11C5/14 ,  G11C7/12 ,  G11C7/10

Abstract: Methods, systems, and devices for input/output line sharing for memory subarrays are described. I/O lines may be shared across subarrays, which may correspond to separate memory tiles. The sharing of I/O lines may allow an I/O line to carry data from one subarray in response to access commands associated with one address range, and to carry data from another subarray in response to access commands associated with another address range. In some cases, sense amplifiers and other components may also be shared across subarrays, including across subarrays in different banks. The sharing of I/O lines may, in some cases, support activating only a subset of subarrays in a bank when accessing data stored in the bank, which may provide power savings.