公开(公告)号：US20230071663A1

公开(公告)日：2023-03-09

申请号：US17943591

申请日：2022-09-13

Applicant: Micron Technology, Inc.

Inventor： Paolo Fantini ,  Andrea Martinelli ,  Claudio Nava

IPC: G11C13/00 ,  H01L27/24 ,  H01L45/00

Abstract: Methods, systems, and devices for decoding architecture for memory tiles are described. Word line tiles of a memory array may each include multiple word line plates, which may each include a sheet of conductive material that includes a first portion extending in a first direction within a plane along with multiple fingers extending in a second direction within the plane. A pillar tile may include one or more pillars that extend vertically between the word line plate fingers. Memory cells may each be couple with a respective word line plate finger and a respective pillar. Word line decoding circuitry, pillar decoding circuitry, or both, may be located beneath the memory array and in some cases may be shared between adjacent pillar tiles.

公开(公告)号：US11144228B2

公开(公告)日：2021-10-12

申请号：US16508729

申请日：2019-07-11

Applicant: Micron Technology, Inc.

Inventor： Andrea Martinelli ,  Christophe Vincent Antoine Laurent ,  Claudio Nava ,  Marco Defendi

IPC: G06F3/06 ,  G11C11/22 ,  G11C29/52 ,  G11C11/4091 ,  G06F11/10 ,  G11C11/408

Abstract: Methods, systems, and devices for circuit partitioning for a memory device are described. In one example, a memory device may include a set of memory tiles that each include a respective array of memory cells (e.g., in an array level or layer). Each of the memory tiles may include a respective circuit level or layer associated with circuitry configured to operate the respective array of memory cells. The memory device may also include circuitry for communicating data between the memory cells of the set of memory tiles and an input/output component. Aspects of the circuitry for communicating the data may be subdivided into repeatable blocks each configured to communicate one or more bits, and the repeatable blocks and other aspects of the circuitry for communicating the data is distributed across the circuit layer of two or more of the set of memory tiles.

公开(公告)号：US20220336015A1

公开(公告)日：2022-10-20

申请号：US17231668

申请日：2021-04-15

Applicant: Micron Technology, Inc.

Inventor： Paolo Fantini ,  Andrea Martinelli ,  Claudio Nava

IPC: G11C13/00 ,  H01L27/24 ,  H01L45/00

Abstract: Methods, systems, and devices for decoding architecture for memory tiles are described. Word line tiles of a memory array may each include multiple word line plates, which may each include a sheet of conductive material that includes a first portion extending in a first direction within a plane along with multiple fingers extending in a second direction within the plane. A pillar tile may include one or more pillars that extend vertically between the word line plate fingers. Memory cells may each be couple with a respective word line plate finger and a respective pillar. Word line decoding circuitry, pillar decoding circuitry, or both, may be located beneath the memory array and in some cases may be shared between adjacent pillar tiles.

公开(公告)号：US11804264B2

公开(公告)日：2023-10-31

申请号：US17943591

申请日：2022-09-13

Applicant: Micron Technology, Inc.

Inventor： Paolo Fantini ,  Andrea Martinelli ,  Claudio Nava

IPC: G11C16/04 ,  G11C13/00 ,  H10B63/00 ,  H10N70/20

CPC classification number: G11C13/0028 ,  G11C13/0004 ,  G11C13/004 ,  H10B63/34 ,  H10B63/845 ,  H10N70/231 ,  G11C2213/75

Abstract: Methods, systems, and devices for decoding architecture for memory tiles are described. Word line tiles of a memory array may each include multiple word line plates, which may each include a sheet of conductive material that includes a first portion extending in a first direction within a plane along with multiple fingers extending in a second direction within the plane. A pillar tile may include one or more pillars that extend vertically between the word line plate fingers. Memory cells may each be couple with a respective word line plate finger and a respective pillar. Word line decoding circuitry, pillar decoding circuitry, or both, may be located beneath the memory array and in some cases may be shared between adjacent pillar tiles.

公开(公告)号：US11475947B1

公开(公告)日：2022-10-18

申请号：US17231668

申请日：2021-04-15

Applicant: Micron Technology, Inc.

Inventor： Paolo Fantini ,  Andrea Martinelli ,  Claudio Nava

IPC: G11C16/04 ,  G11C13/00 ,  H01L27/24 ,  H01L45/00

Abstract: Methods, systems, and devices for decoding architecture for memory tiles are described. Word line tiles of a memory array may each include multiple word line plates, which may each include a sheet of conductive material that includes a first portion extending in a first direction within a plane along with multiple fingers extending in a second direction within the plane. A pillar tile may include one or more pillars that extend vertically between the word line plate fingers. Memory cells may each be couple with a respective word line plate finger and a respective pillar. Word line decoding circuitry, pillar decoding circuitry, or both, may be located beneath the memory array and in some cases may be shared between adjacent pillar tiles.

公开(公告)号：US20220100404A1

公开(公告)日：2022-03-31

申请号：US17493988

申请日：2021-10-05

Applicant: Micron Technology, Inc.

Inventor： Andrea Martinelli ,  Christopher Vincent Antoine Laurent ,  Claudio Nava ,  Marco Defendi

IPC: G06F3/06 ,  G11C11/22 ,  G11C29/52 ,  G11C11/4091 ,  G06F11/10 ,  G11C11/408

Abstract: Methods, systems, and devices for circuit partitioning for a memory device are described. In one example, a memory device may include a set of memory tiles that each include a respective array of memory cells (e.g., in an array level or layer). Each of the memory tiles may include a respective circuit level or layer associated with circuitry configured to operate the respective array of memory cells. The memory device may also include circuitry for communicating data between the memory cells of the set of memory tiles and an input/output component. Aspects of the circuitry for communicating the data may be subdivided into repeatable blocks each configured to communicate one or more bits, and the repeatable blocks and other aspects of the circuitry for communicating the data is distributed across the circuit layer of two or more of the set of memory tiles.

公开(公告)号：US20210011645A1

公开(公告)日：2021-01-14

申请号：US16508729

申请日：2019-07-11

Applicant: Micron Technology, Inc.

Inventor： Andrea Martinelli ,  Christophe Vincent Antoine Laurent ,  Claudio Nava ,  Marco Defendi

IPC: G06F3/06 ,  G11C11/22 ,  G11C11/408 ,  G11C11/4091 ,  G06F11/10 ,  G11C29/52

Abstract: Methods, systems, and devices for circuit partitioning for a memory device are described. In one example, a memory device may include a set of memory tiles that each include a respective array of memory cells (e.g., in an array level or layer). Each of the memory tiles may include a respective circuit level or layer associated with circuitry configured to operate the respective array of memory cells. The memory device may also include circuitry for communicating data between the memory cells of the set of memory tiles and an input/output component. Aspects of the circuitry for communicating the data may be subdivided into repeatable blocks each configured to communicate one or more bits, and the repeatable blocks and other aspects of the circuitry for communicating the data is distributed across the circuit layer of two or more of the set of memory tiles.

公开(公告)号：US12182432B2

公开(公告)日：2024-12-31

申请号：US17493988

申请日：2021-10-05

Applicant: Micron Technology, Inc.

Inventor： Andrea Martinelli ,  Christophe Vincent Antoine Laurent ,  Claudio Nava ,  Marco Defendi

IPC: G11C11/22 ,  G06F3/06 ,  G06F11/10 ,  G11C11/408 ,  G11C11/4091 ,  G11C29/52

Abstract: Methods, systems, and devices for circuit partitioning for a memory device are described. In one example, a memory device may include a set of memory tiles that each include a respective array of memory cells (e.g., in an array level or layer). Each of the memory tiles may include a respective circuit level or layer associated with circuitry configured to operate the respective array of memory cells. The memory device may also include circuitry for communicating data between the memory cells of the set of memory tiles and an input/output component. Aspects of the circuitry for communicating the data may be subdivided into repeatable blocks each configured to communicate one or more bits, and the repeatable blocks and other aspects of the circuitry for communicating the data is distributed across the circuit layer of two or more of the set of memory tiles.