公开(公告)号：US20220108988A1

公开(公告)日：2022-04-07

申请号：US17060457

申请日：2020-10-01

Applicant: Micron Technology, Inc.

Inventor： Byung Yoon Kim ,  Sheng Wei Yang ,  Si-Woo Lee ,  Mark Zaleski

IPC: H01L27/108 ,  H01L27/06 ,  G11C5/10 ,  G11C5/02

Abstract: Systems, methods, and apparatus including conductive line contact regions having multiple multi-direction conductive lines and staircase conductive line contact structures for semiconductor devices. One memory device comprises arrays of vertically stacked memory cells, having multiple multi-direction conductive lines arrays of vertically stacked memory cells, including a vertical stack of layers formed from repeating iterations of a group of layers, the group of layers comprising: a first dielectric material layer, a semiconductor material layer, and a second dielectric material layer, the second dielectric material layer having a conductive line formed in a horizontal plane therein, and the vertical stack of layers having multiple multi-direction conductive lines in an interconnection region with a first portion of the interconnection region formed in an array region and a second portion formed in a conductive line contact region that is spaced from the array region.

公开(公告)号：US20220108987A1

公开(公告)日：2022-04-07

申请号：US17060356

申请日：2020-10-01

Applicant: Micron Technology, Inc.

Inventor： Si-Woo Lee ,  Byung Yoon Kim ,  Kyuseok Lee ,  Sangmin Hwang ,  Mark Zaleski

IPC: H01L27/108 ,  H01L27/06 ,  G11C5/10 ,  G11C5/02

Abstract: Systems, methods, and apparatus including multi-direction conductive lines and staircase contacts for semiconductor devices. One memory device includes an array of vertically stacked memory cells, the array including: a vertical stack of horizontally oriented conductive lines, each conductive line comprising: a first portion extending in a first horizontal direction; and a second portion extending in a second horizontal direction at an angle to the first horizontal direction.

公开(公告)号：US11696432B2

公开(公告)日：2023-07-04

申请号：US17060356

申请日：2020-10-01

Applicant: Micron Technology, Inc.

Inventor： Si-Woo Lee ,  Byung Yoon Kim ,  Kyuseok Lee ,  Sangmin Hwang ,  Mark Zaleski

IPC: H01L27/108 ,  H10B12/00 ,  G11C5/02 ,  G11C5/10 ,  H01L27/06

CPC classification number: H10B12/30 ,  G11C5/025 ,  G11C5/10 ,  H01L27/0688

Abstract: Systems, methods, and apparatus including multi-direction conductive lines and staircase contacts for semiconductor devices. One memory device includes an array of vertically stacked memory cells, the array including: a vertical stack of horizontally oriented conductive lines, each conductive line comprising: a first portion extending in a first horizontal direction; and a second portion extending in a second horizontal direction at an angle to the first horizontal direction.

公开(公告)号：US20240147693A1

公开(公告)日：2024-05-02

申请号：US18403970

申请日：2024-01-04

Applicant: Micron Technology, Inc.

Inventor： Byung Yoon Kim ,  Sheng Wei Yang ,  Si-Woo Lee ,  Mark Zaleski

IPC: H10B12/00 ,  G11C5/02 ,  G11C5/10 ,  H01L27/06

CPC classification number: H10B12/30 ,  G11C5/025 ,  G11C5/10 ,  H01L27/0688 ,  H10B12/02

Abstract: Systems, methods, and apparatus including conductive line contact regions having multiple multi-direction conductive lines and staircase conductive line contact structures for semiconductor devices. One memory device comprises arrays of vertically stacked memory cells, having multiple multi-direction conductive lines arrays of vertically stacked memory cells, including a vertical stack of layers formed from repeating iterations of a group of layers, the group of layers comprising: a first dielectric material layer, a semiconductor material layer, and a second dielectric material layer, the second dielectric material layer having a conductive line formed in a horizontal plane therein, and the vertical stack of layers having multiple multi-direction conductive lines in an interconnection region with a first portion of the interconnection region formed in an array region and a second portion formed in a conductive line contact region that is spaced from the array region.

公开(公告)号：US11903183B2

公开(公告)日：2024-02-13

申请号：US17060457

申请日：2020-10-01

Applicant: Micron Technology, Inc.

Inventor： Byung Yoon Kim ,  Sheng Wei Yang ,  Si-Woo Lee ,  Mark Zaleski

IPC: H01L27/108 ,  H10B12/00 ,  H01L27/06 ,  G11C5/02 ,  G11C5/10

CPC classification number: H10B12/30 ,  G11C5/025 ,  G11C5/10 ,  H01L27/0688 ,  H10B12/02

Abstract: Systems, methods, and apparatus including conductive line contact regions having multiple multi-direction conductive lines and staircase conductive line contact structures for semiconductor devices. One memory device comprises arrays of vertically stacked memory cells, having multiple multi-direction conductive lines arrays of vertically stacked memory cells, including a vertical stack of layers formed from repeating iterations of a group of layers, the group of layers comprising: a first dielectric material layer, a semiconductor material layer, and a second dielectric material layer, the second dielectric material layer having a conductive line formed in a horizontal plane therein, and the vertical stack of layers having multiple multi-direction conductive lines in an interconnection region with a first portion of the interconnection region formed in an array region and a second portion formed in a conductive line contact region that is spaced from the array region.