公开(公告)号：US20230086907A1

公开(公告)日：2023-03-23

申请号：US17888906

申请日：2022-08-16

Applicant: Micron Technology, Inc.

Inventor： Hyunsuk Chun ,  Sheng Wei Yang ,  Shams U. Arifeen

IPC: H01L23/00 ,  H01L23/532 ,  H01L23/58 ,  H01L21/768 ,  H01L23/498

Abstract: Semiconductor devices having metallization structures including crack-inhibiting structures, and associated systems and methods, are disclosed herein. In one embodiment, a semiconductor device includes a metallization structure formed over a semiconductor substrate. The metallization structure can include a bond pad electrically coupled to the semiconductor substrate via one or more layers of conductive material, and an insulating material—such as a low-κ dielectric material—at least partially around the conductive material. The metallization structure can further include a crack-inhibiting structure positioned beneath the bond pad between the bond pad and the semiconductor substrate. The crack-inhibiting structure can include a barrier member extending vertically from the bond pad toward the semiconductor substrate and configured to inhibit crack propagation through the insulating material.

公开(公告)号：US11444037B2

公开(公告)日：2022-09-13

申请号：US17011799

申请日：2020-09-03

Applicant: Micron Technology, Inc.

Inventor： Hyunsuk Chun ,  Sheng Wei Yang ,  Shams U. Arifeen

IPC: H01L23/48 ,  H01L23/52 ,  H01L23/00 ,  H01L23/532 ,  H01L23/58 ,  H01L21/768 ,  H01L23/498

Abstract: Semiconductor devices having metallization structures including crack-inhibiting structures, and associated systems and methods, are disclosed herein. In one embodiment, a semiconductor device includes a metallization structure formed over a semiconductor substrate. The metallization structure can include a bond pad electrically coupled to the semiconductor substrate via one or more layers of conductive material, and an insulating material—such as a low-κ dielectric material—at least partially around the conductive material. The metallization structure can further include a crack-inhibiting structure positioned beneath the bond pad between the bond pad and the semiconductor substrate. The crack-inhibiting structure can include a barrier member extending vertically from the bond pad toward the semiconductor substrate and configured to inhibit crack propagation through the insulating material.

公开(公告)号：US20220108988A1

公开(公告)日：2022-04-07

申请号：US17060457

申请日：2020-10-01

Applicant: Micron Technology, Inc.

Inventor： Byung Yoon Kim ,  Sheng Wei Yang ,  Si-Woo Lee ,  Mark Zaleski

IPC: H01L27/108 ,  H01L27/06 ,  G11C5/10 ,  G11C5/02

Abstract: Systems, methods, and apparatus including conductive line contact regions having multiple multi-direction conductive lines and staircase conductive line contact structures for semiconductor devices. One memory device comprises arrays of vertically stacked memory cells, having multiple multi-direction conductive lines arrays of vertically stacked memory cells, including a vertical stack of layers formed from repeating iterations of a group of layers, the group of layers comprising: a first dielectric material layer, a semiconductor material layer, and a second dielectric material layer, the second dielectric material layer having a conductive line formed in a horizontal plane therein, and the vertical stack of layers having multiple multi-direction conductive lines in an interconnection region with a first portion of the interconnection region formed in an array region and a second portion formed in a conductive line contact region that is spaced from the array region.

公开(公告)号：US20200211982A1

公开(公告)日：2020-07-02

申请号：US16236143

申请日：2018-12-28

Applicant: Micron Technology, Inc.

Inventor： Shams U. Arifeen ,  Hyunsuk Chun ,  Sheng Wei Yang ,  Keizo Kawakita

IPC: H01L23/00

Abstract: Semiconductor devices having metallization structures including crack-inhibiting structures, and associated systems and methods, are disclosed herein. In one embodiment, a semiconductor device includes a metallization structure formed over a semiconductor substrate. The metallization structure can include a bond pad electrically coupled to the semiconductor substrate via one or more layers of conductive material, and an insulating material—such as a low-κ dielectric material—at least partially around the conductive material. The metallization structure can further include a crack-inhibiting structure positioned beneath the bond pad between the bond pad and the semiconductor substrate. The crack-inhibiting structure can include (a) a metal lattice extending laterally between the bond pad and the semiconductor substrate and (b) barrier members extending vertically between the metal lattice and the bond pad.

公开(公告)号：US20240147693A1

公开(公告)日：2024-05-02

申请号：US18403970

申请日：2024-01-04

Applicant: Micron Technology, Inc.

Inventor： Byung Yoon Kim ,  Sheng Wei Yang ,  Si-Woo Lee ,  Mark Zaleski

IPC: H10B12/00 ,  G11C5/02 ,  G11C5/10 ,  H01L27/06

CPC classification number: H10B12/30 ,  G11C5/025 ,  G11C5/10 ,  H01L27/0688 ,  H10B12/02

Abstract: Systems, methods, and apparatus including conductive line contact regions having multiple multi-direction conductive lines and staircase conductive line contact structures for semiconductor devices. One memory device comprises arrays of vertically stacked memory cells, having multiple multi-direction conductive lines arrays of vertically stacked memory cells, including a vertical stack of layers formed from repeating iterations of a group of layers, the group of layers comprising: a first dielectric material layer, a semiconductor material layer, and a second dielectric material layer, the second dielectric material layer having a conductive line formed in a horizontal plane therein, and the vertical stack of layers having multiple multi-direction conductive lines in an interconnection region with a first portion of the interconnection region formed in an array region and a second portion formed in a conductive line contact region that is spaced from the array region.

公开(公告)号：US11903183B2

公开(公告)日：2024-02-13

申请号：US17060457

申请日：2020-10-01

Applicant: Micron Technology, Inc.

Inventor： Byung Yoon Kim ,  Sheng Wei Yang ,  Si-Woo Lee ,  Mark Zaleski

IPC: H01L27/108 ,  H10B12/00 ,  H01L27/06 ,  G11C5/02 ,  G11C5/10

CPC classification number: H10B12/30 ,  G11C5/025 ,  G11C5/10 ,  H01L27/0688 ,  H10B12/02

Abstract: Systems, methods, and apparatus including conductive line contact regions having multiple multi-direction conductive lines and staircase conductive line contact structures for semiconductor devices. One memory device comprises arrays of vertically stacked memory cells, having multiple multi-direction conductive lines arrays of vertically stacked memory cells, including a vertical stack of layers formed from repeating iterations of a group of layers, the group of layers comprising: a first dielectric material layer, a semiconductor material layer, and a second dielectric material layer, the second dielectric material layer having a conductive line formed in a horizontal plane therein, and the vertical stack of layers having multiple multi-direction conductive lines in an interconnection region with a first portion of the interconnection region formed in an array region and a second portion formed in a conductive line contact region that is spaced from the array region.

公开(公告)号：US20210020585A1

公开(公告)日：2021-01-21

申请号：US17062922

申请日：2020-10-05

Applicant: Micron Technology, Inc.

Inventor： Shams U. Arifeen ,  Hyunsuk Chun ,  Sheng Wei Yang ,  Keizo Kawakita

IPC: H01L23/00

Abstract: Semiconductor devices having metallization structures including crack-inhibiting structures, and associated systems and methods, are disclosed herein. In one embodiment, a semiconductor device includes a metallization structure formed over a semiconductor substrate. The metallization structure can include a bond pad electrically coupled to the semiconductor substrate via one or more layers of conductive material, and an insulating material—such as a low-κ dielectric material—at least partially around the conductive material. The metallization structure can further include a crack-inhibiting structure positioned beneath the bond pad between the bond pad and the semiconductor substrate. The crack-inhibiting structure can include (a) a metal lattice extending laterally between the bond pad and the semiconductor substrate and (b) barrier members extending vertically between the metal lattice and the bond pad.

公开(公告)号：US10811365B2

公开(公告)日：2020-10-20

申请号：US16236143

申请日：2018-12-28

Applicant: Micron Technology, Inc.

Inventor： Shams U. Arifeen ,  Hyunsuk Chun ,  Sheng Wei Yang ,  Keizo Kawakita

IPC: H01L23/00

Abstract: Semiconductor devices having metallization structures including crack-inhibiting structures, and associated systems and methods, are disclosed herein. In one embodiment, a semiconductor device includes a metallization structure formed over a semiconductor substrate. The metallization structure can include a bond pad electrically coupled to the semiconductor substrate via one or more layers of conductive material, and an insulating material—such as a low-κ dielectric material—at least partially around the conductive material. The metallization structure can further include a crack-inhibiting structure positioned beneath the bond pad between the bond pad and the semiconductor substrate. The crack-inhibiting structure can include (a) a metal lattice extending laterally between the bond pad and the semiconductor substrate and (b) barrier members extending vertically between the metal lattice and the bond pad.

公开(公告)号：US11848282B2

公开(公告)日：2023-12-19

申请号：US17888906

申请日：2022-08-16

Applicant: Micron Technology, Inc.

Inventor： Hyunsuk Chun ,  Sheng Wei Yang ,  Shams U. Arifeen

IPC: H01L21/76 ,  H01L23/00 ,  H01L23/532 ,  H01L23/58 ,  H01L21/768 ,  H01L23/498

CPC classification number: H01L23/562 ,  H01L21/7682 ,  H01L23/49827 ,  H01L23/5329 ,  H01L23/585 ,  H01L24/05 ,  H01L2224/02235

Abstract: Semiconductor devices having metallization structures including crack-inhibiting structures, and associated systems and methods, are disclosed herein. In one embodiment, a semiconductor device includes a metallization structure formed over a semiconductor substrate. The metallization structure can include a bond pad electrically coupled to the semiconductor substrate via one or more layers of conductive material, and an insulating material—such as a low-κ dielectric material—at least partially around the conductive material. The metallization structure can further include a crack-inhibiting structure positioned beneath the bond pad between the bond pad and the semiconductor substrate. The crack-inhibiting structure can include a barrier member extending vertically from the bond pad toward the semiconductor substrate and configured to inhibit crack propagation through the insulating material.

公开(公告)号：US11616028B2

公开(公告)日：2023-03-28

申请号：US17062922

申请日：2020-10-05

Applicant: Micron Technology, Inc.

Inventor： Shams U. Arifeen ,  Hyunsuk Chun ,  Sheng Wei Yang ,  Keizo Kawakita

IPC: H01L23/00

Abstract: Semiconductor devices having metallization structures including crack-inhibiting structures, and associated systems and methods, are disclosed herein. In one embodiment, a semiconductor device includes a metallization structure formed over a semiconductor substrate. The metallization structure can include a bond pad electrically coupled to the semiconductor substrate via one or more layers of conductive material, and an insulating material—such as a low-κ dielectric material—at least partially around the conductive material. The metallization structure can further include a crack-inhibiting structure positioned beneath the bond pad between the bond pad and the semiconductor substrate. The crack-inhibiting structure can include (a) a metal lattice extending laterally between the bond pad and the semiconductor substrate and (b) barrier members extending vertically between the metal lattice and the bond pad.