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公开(公告)号：US20190096494A1
公开(公告)日：2019-03-28
申请号：US15717554
申请日：2017-09-27
Applicant: Micron Technology, Inc.
Inventor： Aliasgar S. Madraswala , Kristopher H. Gaewsky , Naveen Vittal Prabhu , Purval S. Sule , Trupti Bemalkhedkar , Nehul N. Tailor , Quan H. Ngo , Dheeraj Srinivasan
CPC classification number: G11C16/3459 , G11C11/5628 , G11C16/0458 , G11C16/10 , G11C16/34 , G11C2211/5621 , G11C2211/5644 , G11C2211/5648
Abstract: Various embodiments, disclosed herein, can include apparatus and methods to perform a one check failure byte (CFBYTE) scheme in programming of a memory device. In programming memory cells in which each memory cell can store multiple bits, the multiple bits being a n-tuple of bits of a set of n-tuples of bits with each n-tuple of the set associated with a level of a set of levels of threshold voltages for the memory cells. Verification of a program algorithm can be structured based on a programming algorithm that proceeds in a progressive manner by placing a threshold voltage of one level/distribution at a time. The routine of this progression can be used to perform just one failure byte check for that specific target distribution only, thus eliminating the need to check failure byte for all subsequent target distribution during every stage of program algorithm. Additional apparatus, systems, and methods are disclosed.
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公开(公告)号：US10762974B2
公开(公告)日：2020-09-01
申请号：US16430086
申请日：2019-06-03
Applicant: Micron Technology, Inc.
Inventor： Aliasgar S. Madraswala , Kristopher H. Gaewsky , Naveen Vittal Prabhu , Purval S. Sule , Trupti Bemalkhedkar , Nehul N. Tailor , Quan H. Ngo , Dheeraj Srinivasan
Abstract: Various embodiments, disclosed herein, can include apparatus and methods to perform a one check failure byte (CFBYTE) scheme in programming of a memory device. In programming memory cells in which each memory cell can store multiple bits, the multiple bits being a n-tuple of bits of a set of n-tuples of bits with each n-tuple of the set associated with a level of a set of levels of threshold voltages for the memory cells. Verification of a program algorithm can be structured based on a programming algorithm that proceeds in a progressive manner by placing a threshold voltage of one level/distribution at a time. The routine of this progression can be used to perform just one failure byte check for that specific target distribution only, thus eliminating the need to check failure byte for all subsequent target distribution during every stage of program algorithm. Additional apparatus, systems, and methods are disclosed.
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公开(公告)号：US10354738B2
公开(公告)日：2019-07-16
申请号：US15717554
申请日：2017-09-27
Applicant: Micron Technology, Inc.
Inventor： Aliasgar S. Madraswala , Kristopher H. Gaewsky , Naveen Vittal Prabhu , Purval S. Sule , Trupti Bemalkhedkar , Nehul N. Tailor , Quan H. Ngo , Dheeraj Srinivasan
Abstract: Various embodiments, disclosed herein, can include apparatus and methods to perform a one check failure byte (CFBYTE) scheme in programming of a memory device. In programming memory cells in which each memory cell can store multiple bits, the multiple bits being a n-tuple of bits of a set of n-tuples of bits with each n-tuple of the set associated with a level of a set of levels of threshold voltages for the memory cells. Verification of a program algorithm can be structured based on a programming algorithm that proceeds in a progressive manner by placing a threshold voltage of one level/distribution at a time. The routine of this progression can be used to perform just one failure byte check for that specific target distribution only, thus eliminating the need to check failure byte for all subsequent target distribution during every stage of program algorithm. Additional apparatus, systems, and methods are disclosed.
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