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公开(公告)号：US10777277B2
公开(公告)日：2020-09-15
申请号：US16655826
申请日：2019-10-17
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Violante Moschiano , Purval S. Sule , Han Liu , Andrea D'Alessandro , Pranav Kalavade , Han Zhao , Shantanu Rajwade
IPC: G11C16/12 , G11C11/4074 , G11C16/04 , G11C16/34 , G11C5/06
Abstract: Memories having a controller configured to perform methods during programming operations including applying a first voltage level to first and second data lines while applying a second, lower, voltage level to first and second select gates connected between the data lines and respective strings of memory cells; decreasing a voltage level of the first data line to a third voltage level; increasing a voltage level of the first select gate to a fourth voltage level; applying a fifth voltage level, higher than the first voltage level, to first and second access lines coupled to memory cells of the strings of memory cells; and increasing a voltage level of the first access line to a sixth voltage level.
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公开(公告)号：US20200066350A1
公开(公告)日：2020-02-27
申请号：US16655826
申请日：2019-10-17
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Violante Moschiano , Purval S. Sule , Han Liu , Andrea D'Alessandro , Pranav Kalavade , Han Zhao , Shantanu Rajwade
IPC: G11C16/12 , G11C16/34 , G11C11/4074 , G11C5/06 , G11C16/04
Abstract: Memories having a controller configured to perform methods during programming operations including applying a first voltage level to first and second data lines while applying a second, lower, voltage level to first and second select gates connected between the data lines and respective strings of memory cells; decreasing a voltage level of the first data line to a third voltage level; increasing a voltage level of the first select gate to a fourth voltage level; applying a fifth voltage level, higher than the first voltage level, to first and second access lines coupled to memory cells of the strings of memory cells; and increasing a voltage level of the first access line to a sixth voltage level.
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公开(公告)号：US20190096494A1
公开(公告)日：2019-03-28
申请号：US15717554
申请日：2017-09-27
Applicant: Micron Technology, Inc.
Inventor： Aliasgar S. Madraswala , Kristopher H. Gaewsky , Naveen Vittal Prabhu , Purval S. Sule , Trupti Bemalkhedkar , Nehul N. Tailor , Quan H. Ngo , Dheeraj Srinivasan
CPC classification number: G11C16/3459 , G11C11/5628 , G11C16/0458 , G11C16/10 , G11C16/34 , G11C2211/5621 , G11C2211/5644 , G11C2211/5648
Abstract: Various embodiments, disclosed herein, can include apparatus and methods to perform a one check failure byte (CFBYTE) scheme in programming of a memory device. In programming memory cells in which each memory cell can store multiple bits, the multiple bits being a n-tuple of bits of a set of n-tuples of bits with each n-tuple of the set associated with a level of a set of levels of threshold voltages for the memory cells. Verification of a program algorithm can be structured based on a programming algorithm that proceeds in a progressive manner by placing a threshold voltage of one level/distribution at a time. The routine of this progression can be used to perform just one failure byte check for that specific target distribution only, thus eliminating the need to check failure byte for all subsequent target distribution during every stage of program algorithm. Additional apparatus, systems, and methods are disclosed.
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公开(公告)号：US10762974B2
公开(公告)日：2020-09-01
申请号：US16430086
申请日：2019-06-03
Applicant: Micron Technology, Inc.
Inventor： Aliasgar S. Madraswala , Kristopher H. Gaewsky , Naveen Vittal Prabhu , Purval S. Sule , Trupti Bemalkhedkar , Nehul N. Tailor , Quan H. Ngo , Dheeraj Srinivasan
Abstract: Various embodiments, disclosed herein, can include apparatus and methods to perform a one check failure byte (CFBYTE) scheme in programming of a memory device. In programming memory cells in which each memory cell can store multiple bits, the multiple bits being a n-tuple of bits of a set of n-tuples of bits with each n-tuple of the set associated with a level of a set of levels of threshold voltages for the memory cells. Verification of a program algorithm can be structured based on a programming algorithm that proceeds in a progressive manner by placing a threshold voltage of one level/distribution at a time. The routine of this progression can be used to perform just one failure byte check for that specific target distribution only, thus eliminating the need to check failure byte for all subsequent target distribution during every stage of program algorithm. Additional apparatus, systems, and methods are disclosed.
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公开(公告)号：US10354738B2
公开(公告)日：2019-07-16
申请号：US15717554
申请日：2017-09-27
Applicant: Micron Technology, Inc.
Inventor： Aliasgar S. Madraswala , Kristopher H. Gaewsky , Naveen Vittal Prabhu , Purval S. Sule , Trupti Bemalkhedkar , Nehul N. Tailor , Quan H. Ngo , Dheeraj Srinivasan
Abstract: Various embodiments, disclosed herein, can include apparatus and methods to perform a one check failure byte (CFBYTE) scheme in programming of a memory device. In programming memory cells in which each memory cell can store multiple bits, the multiple bits being a n-tuple of bits of a set of n-tuples of bits with each n-tuple of the set associated with a level of a set of levels of threshold voltages for the memory cells. Verification of a program algorithm can be structured based on a programming algorithm that proceeds in a progressive manner by placing a threshold voltage of one level/distribution at a time. The routine of this progression can be used to perform just one failure byte check for that specific target distribution only, thus eliminating the need to check failure byte for all subsequent target distribution during every stage of program algorithm. Additional apparatus, systems, and methods are disclosed.
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Patent Agency Ranking
公开(公告)号：US11721396B2
公开(公告)日：2023-08-08
申请号：US17012442
申请日：2020-09-04
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Violante Moschiano , Purval S. Sule , Han Liu , Andrea D'Alessandro , Pranav Kalavade , Han Zhao , Shantanu Rajwade
IPC: G11C16/12 , G11C11/4074 , G11C16/04 , G11C16/34 , G11C5/06
CPC classification number: G11C16/12 , G11C5/063 , G11C11/4074 , G11C16/0483 , G11C16/3427
Abstract: Memories having a controller configured to perform methods during programming operations including apply a first voltage level to a data line selectively connected to a selected memory cell selected, apply a lower second voltage level to a select gate connected between the data line and the memory cell, decrease the voltage level applied to the data line from the first voltage level to a third voltage level while continuing to apply the second voltage level to the select gate, increase the voltage level applied to the select gate from the second voltage level to a fourth voltage level after the voltage level of the data line settles to the third voltage level, and apply a programming voltage to the memory cell after increasing the voltage level applied to the select gate to the fourth voltage level.
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公开(公告)号：US11210025B2
公开(公告)日：2021-12-28
申请号：US16725098
申请日：2019-12-23
Applicant: Micron Technology, Inc.
Inventor： Aliasgar S. Madraswala , Purval S. Sule , Karthikeyan Ramamurthi
Abstract: Some embodiments include apparatuses and methods using memory cells and a control unit to suspend an erase operation performed on a first portion of the memory cells and to suspend a program operation performed on a second portion of the memory cells while the erase operation is suspended. The control unit includes register circuitry to store status information indicating that the program operation is suspended while the erase operation is suspended.
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公开(公告)号：US10514862B2
公开(公告)日：2019-12-24
申请号：US15216097
申请日：2016-07-21
Applicant: Micron Technology, Inc.
Inventor： Aliasgar S. Madraswala , Purval S. Sule , Karthikeyan Ramamurthi
Abstract: Some embodiments include apparatuses and methods using memory cells and a control unit to suspend an erase operation performed on a first portion of the memory cells and to suspend a program operation performed on a second portion of the memory cells while the erase operation is suspended. The control unit includes register circuitry to store status information indicating that the program operation is suspended while the erase operation is suspended.
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公开(公告)号：US10482974B1
公开(公告)日：2019-11-19
申请号：US16106185
申请日：2018-08-21
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Violante Moschiano , Purval S. Sule , Han Liu , Andrea D'Alessandro , Pranav Kalavade , Han Zhao , Shantanu Rajwade
Abstract: Methods include applying a first voltage level to first and second data lines while applying a second, lower, voltage level to first and second select gates connected between the data lines and respective strings of memory cells; decreasing a voltage level of the first data line to a third voltage level; increasing a voltage level of the first select gate to a fourth voltage level; applying a fifth voltage level, higher than the first voltage level, to first and second access lines coupled to memory cells of the strings of memory cells; and increasing a voltage level of the first access line to a sixth voltage level.
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公开(公告)号：US20180024772A1
公开(公告)日：2018-01-25
申请号：US15216097
申请日：2016-07-21
Applicant: Micron Technology, Inc.
Inventor： Aliasgar S. Madraswala , Purval S. Sule , Karthikeyan Ramamurthi
Abstract: Some embodiments include apparatuses and methods using memory cells and a control unit to suspend an erase operation performed on a first portion of the memory cells and to suspend a program operation performed on a second portion of the memory cells while the erase operation is suspended. The control unit includes register circuitry to store status information indicating that the program operation is suspended while the erase operation is suspended.
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