公开(公告)号：US20210126193A1

公开(公告)日：2021-04-29

申请号：US16665679

申请日：2019-10-28

Applicant: Micron Technology, Inc.

Inventor： Santanu Sarkar ,  Robert K. Grubbs ,  Farrell M. Good ,  Adam W. Saxler ,  Andrea Gotti

IPC: H01L45/00

Abstract: An electronic device comprising a stack structure comprising one or more stacks of materials and a metal oxide material adjacent to the stacks of materials. The materials of the stacks comprise one or more chalcogenide materials. The metal oxide material comprises aluminum oxide, aluminum silicate, hafnium oxide, hafnium silicate, zirconium oxide, zirconium silicate, or a combination thereof and the metal oxide material extends continuously from an upper portion of the one or more stacks of materials to a lower portion of the one or more stacks of materials. Additional electronic devices are disclosed, as are related systems and methods of forming an electronic device.

公开(公告)号：US11984382B2

公开(公告)日：2024-05-14

申请号：US17492185

申请日：2021-10-01

Applicant: Micron Technology, Inc.

Inventor： Pengyuan Zheng ,  David Ross Economy ,  Yongjun J. Hu ,  Kent H. Zhuang ,  Robert K. Grubbs

IPC: H01L23/373 ,  H01L21/02 ,  H01L21/768 ,  H01L23/535

CPC classification number: H01L23/3736 ,  H01L21/02186 ,  H01L21/0234 ,  H01L21/768 ,  H01L23/535

Abstract: Methods, systems, and devices related to a memory device with a thermal barrier are described. The thermal barrier (e.g., a low density thermal barrier) may be positioned between an access line (e.g., a digit line or a word line) and a cell component. The thermal barrier may be formed on the surface of a barrier material by applying a plasma treatment to the barrier material. The thermal barrier may have a lower density than the barrier material and may be configured to thermally insulate the cell component from thermal energy generated in the memory device, among other benefits.

公开(公告)号：US11980108B2

公开(公告)日：2024-05-07

申请号：US17881285

申请日：2022-08-04

Applicant: Micron Technology, Inc.

Inventor： Farrell M. Good ,  Robert K. Grubbs ,  Gurpreet S. Lugani

IPC: H10N70/00

CPC classification number: H10N70/063 ,  H10N70/826 ,  H10N70/882

Abstract: Techniques are described to form a liner to protect a material, such as a storage element material, from damage during subsequent operations or phases of a manufacturing process. The liner may be bonded to the material (e.g., a chalcogenide material) using a strong bond or a weak bond. In some cases, a sealant material may be deposited during an etching phase of the manufacturing process to prevent subsequent etching operations from damaging a material that has just been etched.

公开(公告)号：US20220376176A1

公开(公告)日：2022-11-24

申请号：US17818313

申请日：2022-08-08

Applicant: Micron Technology, Inc.

Inventor： Santanu Sarkar ,  Robert K. Grubbs ,  Farrell M. Good ,  Adam W. Saxler ,  Andrea Gotti

IPC: H01L45/00 ,  H01L27/24

Abstract: An electronic device comprising a stack structure comprising one or more stacks of materials and a metal oxide material adjacent to the stacks of materials. The materials of the stacks comprise one or more chalcogenide materials. The metal oxide material comprises aluminum oxide, aluminum silicate, hafnium oxide, hafnium silicate, zirconium oxide, zirconium silicate, or a combination thereof and the metal oxide material extends continuously from an upper portion of the one or more stacks of materials to a lower portion of the one or more stacks of materials. Additional electronic devices are disclosed, as are related systems and methods of forming an electronic device.

公开(公告)号：US11444243B2

公开(公告)日：2022-09-13

申请号：US16665679

申请日：2019-10-28

Applicant: Micron Technology, Inc.

Inventor： Santanu Sarkar ,  Robert K. Grubbs ,  Farrell M. Good ,  Adam W. Saxler ,  Andrea Gotti

IPC: H01L45/00

Abstract: An electronic device comprising a stack structure comprising one or more stacks of materials and a metal oxide material adjacent to the stacks of materials. The materials of the stacks comprise one or more chalcogenide materials. The metal oxide material comprises aluminum oxide, aluminum silicate, hafnium oxide, hafnium silicate, zirconium oxide, zirconium silicate, or a combination thereof and the metal oxide material extends continuously from an upper portion of the one or more stacks of materials to a lower portion of the one or more stacks of materials. Additional electronic devices are disclosed, as are related systems and methods of forming an electronic device.

公开(公告)号：US20220238324A1

公开(公告)日：2022-07-28

申请号：US17248376

申请日：2021-01-22

Applicant: Micron Technology, Inc.

Inventor： Farrell M. Good ,  Robert K. Grubbs

IPC: H01L21/02 ,  C23C16/455 ,  C23C16/448 ,  C23C16/50 ,  C23C16/34

Abstract: A method of forming a microelectronic device comprises treating a base structure with a first precursor to adsorb the first precursor to a surface of the base structure and form a first material. The first precursor comprises a hydrazine-based compound including Si—N—Si bonds. The first material is treated with a second precursor to covert the first material into a second material. The second precursor comprises a Si-centered radical. The second material is treaded with a third precursor to covert the second material into a third material comprising Si and N. The third precursor comprises an N-centered radical. An ALD system and a method of forming a seal material through ALD are also described.

公开(公告)号：US20220020662A1

公开(公告)日：2022-01-20

申请号：US17492185

申请日：2021-10-01

Applicant: Micron Technology, Inc.

Inventor： Pengyuan Zheng ,  David Ross Economy ,  Yongjun J. Hu ,  Kent H. Zhuang ,  Robert K. Grubbs

IPC: H01L23/373 ,  H01L23/535 ,  H01L21/768 ,  H01L21/02

Abstract: Methods, systems, and devices related to a memory device with a thermal barrier are described. The thermal barrier (e.g., a low density thermal barrier) may be positioned between an access line (e.g., a digit line or a word line) and a cell component. The thermal barrier may be formed on the surface of a barrier material by applying a plasma treatment to the barrier material. The thermal barrier may have a lower density than the barrier material and may be configured to thermally insulate the cell component from thermal energy generated in the memory device, among other benefits.

公开(公告)号：US20240347418A1

公开(公告)日：2024-10-17

申请号：US18640682

申请日：2024-04-19

Applicant: Micron Technology, Inc.

Inventor： Pengyuan Zheng ,  David Ross Economy ,  Yongjun J. Hu ,  Kent H. Zhuang ,  Robert K. Grubbs

IPC: H01L23/373 ,  H01L21/02 ,  H01L21/768 ,  H01L23/535

CPC classification number: H01L23/3736 ,  H01L21/02186 ,  H01L21/0234 ,  H01L21/768 ,  H01L23/535

Abstract: Methods, systems, and devices related to a memory device with a thermal barrier are described. The thermal barrier (e.g., a low density thermal barrier) may be positioned between an access line (e.g., a digit line or a word line) and a cell component. The thermal barrier may be formed on the surface of a barrier material by applying a plasma treatment to the barrier material. The thermal barrier may have a lower density than the barrier material and may be configured to thermally insulate the cell component from thermal energy generated in the memory device, among other benefits.

公开(公告)号：US11158561B2

公开(公告)日：2021-10-26

申请号：US16400956

申请日：2019-05-01

Applicant: Micron Technology, Inc.

Inventor： Pengyuan Zheng ,  David Ross Economy ,  Yongjun J. Hu ,  Kent H. Zhuang ,  Robert K. Grubbs

IPC: H01L23/373 ,  H01L23/535 ,  H01L21/768 ,  H01L21/02

Abstract: Methods, systems, and devices related to a memory device with a thermal barrier are described. The thermal barrier (e.g., a low density thermal barrier) may be positioned between an access line (e.g., a digit line or a word line) and a cell component. The thermal barrier may be formed on the surface of a barrier material by applying a plasma treatment to the barrier material. The thermal barrier may have a lower density than the barrier material and may be configured to thermally insulate the cell component from thermal energy generated in the memory device, among other benefits.

公开(公告)号：US20210202841A1

公开(公告)日：2021-07-01

申请号：US16731963

申请日：2019-12-31

Applicant: Micron Technology, Inc.

Inventor： Farrell M. Good ,  Robert K. Grubbs ,  Gurpreet S. Lugani

IPC: H01L45/00

Abstract: Techniques are described to form a liner to protect a material, such as a storage element material, from damage during subsequent operations or phases of a manufacturing process. The liner may be bonded to the material (e.g., a chalcogenide material) using a strong bond or a weak bond. In some cases, a sealant material may be deposited during an etching phase of the manufacturing process to prevent subsequent etching operations from damaging a material that has just been etched.