公开(公告)号：US20220093165A1

公开(公告)日：2022-03-24

申请号：US17030018

申请日：2020-09-23

Applicant: MICRON TECHNOLOGY, INC.

Inventor： SHINGO MITSUBORI ,  HIDEKAZU NOGUCHI

IPC: G11C11/406

Abstract: Embodiments of the disclosure are drawn to apparatuses and methods for controlling refresh operations. Responsive to a refresh command, or one or more pumps generated responsive to the refresh command, different banks of a memory array may perform different types of refresh operations for a pump. In some examples, the type of refresh operation performed by a bank may vary from pump to pump of a refresh operation.

公开(公告)号：US20240013823A1

公开(公告)日：2024-01-11

申请号：US17860064

申请日：2022-07-07

Applicant: Micron Technology, Inc.

Inventor： SHINGO MITSUBORI ,  RYO FUJIMAKI ,  YUTAKA UEMURA

IPC: G11C7/22 ,  G11C7/10

CPC classification number: G11C7/222 ,  G11C7/1039 ,  G11C7/1045 ,  G11C7/1093

Abstract: Apparatuses for timing control in a write path are disclosed. An example apparatus includes: a clock input circuit that receives a clock signal and provides an internal clock signal; a command decoder that receives command signals and the internal clock signal, and provides an active write command signal when the command signals indicates a write operation; a write latency shifter that receives the write command signal, a latency value and a WICA value, adjusts timing of the write command signal responsive to the latency value and the WICA value, and provides a shifted write command signal; and a write DLL including a delay line that receives the shifted write command signal and provides a delayed write command signal. The write DLL provides the WICA value to set a propagation time from the clock input circuit to the write DLL to be a multiple of a period of the clock signal.

公开(公告)号：US20150120997A1

公开(公告)日：2015-04-30

申请号：US14523704

申请日：2014-10-24

Applicant: Micron Technology, Inc.

Inventor： SHINGO MITSUBORI ,  Hiroki Fujisawa

IPC: G11C7/10

CPC classification number: G11C5/025 ,  G11C7/08 ,  G11C7/1048 ,  G11C7/1051 ,  G11C7/1069 ,  G11C7/12 ,  G11C11/4091 ,  G11C11/4094 ,  G11C11/4096

Abstract: A semiconductor memory disclosed in this disclosure includes first and second memory cell arrays, a first main data line that transfers the read data read from the first memory cell array, a second main data line that transfers the read data read from the second memory cell array, a main amplifier coupled to the second main data line, and a repeater circuit coupled to the first main data line and the second main data line.

Abstract translation: 本公开中公开的半导体存储器包括第一和第二存储器单元阵列，传送从第一存储单元阵列读取的读取数据的第一主数据线，传送从第二存储单元阵列读取的读取数据的第二主数据线 耦合到第二主数据线的主放大器，以及耦合到第一主数据线和第二主数据线的中继器电路。