公开(公告)号：US20230386529A1

公开(公告)日：2023-11-30

申请号：US17752573

申请日：2022-05-24

Applicant: MICRON TECHNOLOGY, INC.

Inventor： YUTAKA UEMURA ,  YOSHIYA KOMATSU

IPC: G11C7/10 ,  H03K3/0233

CPC classification number: G11C7/1039 ,  G11C7/1093 ,  G11C7/1066 ,  H03K3/0233

Abstract: In some examples, command decoders may have multiple command paths. In some examples, command signals from one command path may be provided to another command path from a node located between two latches of the command decoder, such as two latches of a flip-flop. In some examples, the command decoder may include separate flip-flops for different command modes. In some examples, the separate flip-flops may be tristate flip-flops. In some examples, the command decoder may include alternate logic circuits rather than a multiplexer.

公开(公告)号：US20240013823A1

公开(公告)日：2024-01-11

申请号：US17860064

申请日：2022-07-07

Applicant: Micron Technology, Inc.

Inventor： SHINGO MITSUBORI ,  RYO FUJIMAKI ,  YUTAKA UEMURA

IPC: G11C7/22 ,  G11C7/10

CPC classification number: G11C7/222 ,  G11C7/1039 ,  G11C7/1045 ,  G11C7/1093

Abstract: Apparatuses for timing control in a write path are disclosed. An example apparatus includes: a clock input circuit that receives a clock signal and provides an internal clock signal; a command decoder that receives command signals and the internal clock signal, and provides an active write command signal when the command signals indicates a write operation; a write latency shifter that receives the write command signal, a latency value and a WICA value, adjusts timing of the write command signal responsive to the latency value and the WICA value, and provides a shifted write command signal; and a write DLL including a delay line that receives the shifted write command signal and provides a delayed write command signal. The write DLL provides the WICA value to set a propagation time from the clock input circuit to the write DLL to be a multiple of a period of the clock signal.

公开(公告)号：US20230386555A1

公开(公告)日：2023-11-30

申请号：US17825600

申请日：2022-05-26

Applicant: MICRON TECHNOLOGY, INC.

Inventor： YOSHIYA KOMATSU ,  YUTAKA UEMURA

IPC: G11C11/4076 ,  G11C11/4074 ,  G11C11/4093

CPC classification number: G11C11/4076 ,  G11C11/4074 ,  G11C11/4093

Abstract: Apparatuses, systems, and methods for bias temperature instability (BTI) mitigation. A BTI oscillator provides a periodic BTI signal. A BTI logic circuit generates a BTI pulse signal based on the periodic BTI signal and synchronized to a clock signal. A clock gating circuit passes the clock signal to a clock path when the periodic BTI signal is active. When the memory is in an unclocked mode, where an external clock is not received, the periodic BTI signal is provided to a clock input buffer and passed as the clock signal.

公开(公告)号：US20230386530A1

公开(公告)日：2023-11-30

申请号：US17752605

申请日：2022-05-24

Applicant: MICRON TECHNOLOGY, INC.

Inventor： YUTAKA UEMURA ,  YOSHIYA KOMATSU

IPC: G11C7/10 ,  H03K19/173 ,  H03K19/20

CPC classification number: G11C7/1039 ,  G11C7/1063 ,  G11C7/109 ,  H03K19/1737 ,  H03K19/20

Abstract: In some examples, command decoders may have multiple command paths. In some examples, command signals from one command path may be provided to another command path from a node located between two latches of the command decoder, such as two latches of a flip-flop. In some examples, the command decoder may include separate flip-flops for different command modes. In some examples, the separate flip-flops may be tristate flip-flops. In some examples, the command decoder may include alternate logic circuits rather than a multiplexer.