公开(公告)号：US11322194B2

公开(公告)日：2022-05-03

申请号：US17147976

申请日：2021-01-13

Applicant: Micron Technology, Inc.

Inventor： Minoru Someya ,  Yukihide Suzuki ,  Sadayuki Okuma

IPC: G11C8/00 ,  G11C11/408 ,  G11C11/409 ,  G11C7/10 ,  G11C7/22 ,  G11C11/4074

Abstract: Compensating for offsets in buffers and related systems, methods, and devices are disclosed. An apparatus includes buffers, control circuitry, and fuses. Each of the buffers includes an output and an offset adjustment input. Each of the buffers is controllable to adjust a direct current offset of an output voltage potential responsive to an offset adjustment code provided to the offset adjustment input. The control circuitry includes sets of offset latches. The offset adjustment input of each of the buffers is operably coupled to a different one of the sets of offset latches. Each set of offset latches is configured to provide the offset adjustment code to the offset adjustment input of a corresponding buffer. The fuses are configured to provide the offset adjustment code to each of a subset of the sets of offset latches.

公开(公告)号：US10937486B1

公开(公告)日：2021-03-02

申请号：US16598905

申请日：2019-10-10

Applicant: Micron Technology, Inc.

Inventor： Minoru Someya ,  Yukihide Suzuki ,  Sadayuki Okuma

IPC: G11C8/00 ,  G11C11/408 ,  G11C11/409 ,  G11C7/10 ,  G11C7/22 ,  G11C11/4074

Abstract: Compensating for offsets in buffers and related systems, methods, and devices are disclosed. An apparatus includes buffers, control circuitry, and fuses. Each of the buffers includes an output and an offset adjustment input. Each of the buffers is controllable to adjust a direct current offset of an output voltage potential responsive to an offset adjustment code provided to the offset adjustment input. The control circuitry includes sets of offset latches. The offset adjustment input of each of the buffers is operably coupled to a different one of the sets of offset latches. Each set of offset latches is configured to provide the offset adjustment code to the offset adjustment input of a corresponding buffer. The fuses are configured to provide the offset adjustment code to each of a subset of the sets of offset latches.

公开(公告)号：US20220351797A1

公开(公告)日：2022-11-03

申请号：US17243086

申请日：2021-04-28

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Sadayuki Okuma

IPC: G11C29/38 ,  G11C17/16 ,  G11C17/18 ,  G11C11/4096 ,  G11C11/4093 ,  G11C29/14

Abstract: Disclosed herein is an apparatus that includes a data terminal, a memory cell array, a mode register storing a plurality of operation parameters, and an output circuit configured to output, in response to a read command, an incorrect data to the data terminal instead of a correct data read from the memory cell array when a predetermined one of the operation parameters indicates a test mode.

公开(公告)号：US10943637B2

公开(公告)日：2021-03-09

申请号：US16234397

申请日：2018-12-27

Applicant: Micron Technology, Inc.

Inventor： Sadayuki Okuma

IPC: G11C11/406 ,  G06F12/06

Abstract: An apparatus includes an address bus configured to convey a command address; a primary address latch connected to the address bus and configured to latch a first address; a primary counter connected to the primary address latch and configured to track a primary count value when the command address matches the first address; and a secondary counter connected to the primary counter and configured to update a secondary count value when the primary count value reaches a primary threshold.

公开(公告)号：US11610623B2

公开(公告)日：2023-03-21

申请号：US17168049

申请日：2021-02-04

Applicant: Micron Technology, Inc.

Inventor： Sadayuki Okuma

IPC: G11C11/406 ,  G06F12/06 ,  G11C11/408

Abstract: A refresh tracking circuit and associated methods are disclosed herein. The tracking circuit may be configured to track a primary count value and a secondary count value based on addresses associated with received commands. The primary and secondary count values may be configured to control corresponding refresh operations respectively associated with a primary address and a secondary address.

公开(公告)号：US09792964B1

公开(公告)日：2017-10-17

申请号：US15270996

申请日：2016-09-20

Applicant: Micron Technology, Inc.

Inventor： Sadayuki Okuma

IPC: G11C7/10 ,  G11C5/14 ,  G11C29/12

CPC classification number: G11C7/1084 ,  G11C5/147 ,  G11C7/1045 ,  G11C29/12005 ,  G11C29/1201 ,  G11C29/12015

Abstract: Apparatuses for providing external terminals of a semiconductor device are described. An example apparatus includes an input pad, an input buffer including a first input node and a second input node, a switch that couples the first input node and the second input node in an active state and further decouples the first input node and the second input node in an inactive state, a control circuit that provides a signal causing the switch to be in the active state or an inactive state. The first input node of the input buffer is coupled to the input pad by a conductive wiring.

公开(公告)号：US20180082721A1

公开(公告)日：2018-03-22

申请号：US15702848

申请日：2017-09-13

Applicant: Micron Technology, Inc.

Inventor： Sadayuki Okuma

IPC: G11C7/10 ,  G11C29/12 ,  G11C5/14

CPC classification number: G11C7/1084 ,  G11C5/147 ,  G11C7/1045 ,  G11C29/12005 ,  G11C29/1201 ,  G11C29/12015

Abstract: Apparatuses for providing external terminals of a semiconductor device are described. An example apparatus includes an input pad, an input buffer including a first input node and a second input node, a switch that couples the first input node and the second input node in an active state and further decouples the first input node and the second input node in an inactive state, a control circuit that provides a signal causing the switch to be in the active state or an inactive state. The first input node of the input buffer is coupled to the input pad by a conductive wiring.

公开(公告)号：US11810634B2

公开(公告)日：2023-11-07

申请号：US17243086

申请日：2021-04-28

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Sadayuki Okuma

IPC: G11C29/00 ,  G11C29/38 ,  G11C17/16 ,  G11C29/14 ,  G11C11/4096 ,  G11C11/4093 ,  G11C17/18

CPC classification number: G11C29/38 ,  G11C11/4093 ,  G11C11/4096 ,  G11C17/16 ,  G11C17/18 ,  G11C29/14

Abstract: Disclosed herein is an apparatus that includes a data terminal, a memory cell array, a mode register storing a plurality of operation parameters, and an output circuit configured to output, in response to a read command, an incorrect data to the data terminal instead of a correct data read from the memory cell array when a predetermined one of the operation parameters indicates a test mode.

公开(公告)号：US20210158862A1

公开(公告)日：2021-05-27

申请号：US17168049

申请日：2021-02-04

Applicant: Micron Technology, Inc.

Inventor： Sadayuki Okuma

IPC: G11C11/406 ,  G06F12/06

Abstract: A refresh tracking circuit and associated methods are disclosed herein. The tracking circuit may be configured to track a primary count value and a secondary count value based on addresses associated with received commands. The primary and secondary count values may be configured to control corresponding refresh operations respectively associated with a primary address and a secondary address.

公开(公告)号：US20210134350A1

公开(公告)日：2021-05-06

申请号：US17147976

申请日：2021-01-13

Applicant: Micron Technology, Inc.

Inventor： Minoru Someya ,  Yukihide Suzuki ,  Sadayuki Okuma

IPC: G11C11/408 ,  G11C11/409 ,  G11C11/4074 ,  G11C7/10 ,  G11C7/22

Abstract: Compensating for offsets in buffers and related systems, methods, and devices are disclosed. An apparatus includes buffers, control circuitry, and fuses. Each of the buffers includes an output and an offset adjustment input. Each of the buffers is controllable to adjust a direct current offset of an output voltage potential responsive to an offset adjustment code provided to the offset adjustment input. The control circuitry includes sets of offset latches. The offset adjustment input of each of the buffers is operably coupled to a different one of the sets of offset latches. Each set of offset latches is configured to provide the offset adjustment code to the offset adjustment input of a corresponding buffer. The fuses are configured to provide the offset adjustment code to each of a subset of the sets of offset latches.