公开(公告)号：US20240403165A1

公开(公告)日：2024-12-05

申请号：US18667799

申请日：2024-05-17

Applicant: Micron Technology, Inc.

Inventor： Nathan A. Eckel ,  James Brian Johnson ,  Paul A. Laberge

IPC: G06F11/10 ,  G06F11/14

Abstract: Methods, systems, and devices for information broadcast techniques for stacked memory architectures are described. A semiconductor system may include multiple instances of interface circuitry of a semiconductor die that are each operable for accessing a respective set of one or more memory arrays of one or more other semiconductor dies, as well as read-only storage for storing information that is common to the multiple instances of the interface circuitry. In some implementations, such read-only storage may include one-time programmable memory elements (e.g., fuses, antifuses) that are located in at least one of the one or more other semiconductor dies, and are accessible by each of the multiple instances of interface circuitry. The read-only storage may store information that supports common aspects of interface circuitry operations such as initialization operations, evaluation operations, configuration operations, access operations, or other operations, which may be broadcast to the multiple instances of interface circuitry.

公开(公告)号：US20240303157A1

公开(公告)日：2024-09-12

申请号：US18584385

申请日：2024-02-22

Applicant: Micron Technology, Inc.

Inventor： Scott E. Schaefer ,  Paul A. Laberge

IPC: G06F11/10 ,  G06F11/07

CPC classification number: G06F11/1068 ,  G06F11/0787 ,  G06F11/079

Abstract: Methods, systems, and devices for memory die fault detection using a calibration pin are described. A memory device may perform a calibration procedure on a first resistor of each of a set of memory dies of a memory module using a pin coupled with the memory module. The memory device may couple the pin to a second resistor of a memory die of the set of memory dies based on the memory die identifying a fault condition for the memory die executing one or more of multiple commands from the host device. The memory device may receive, from the host device, a command to read a register of one or more memory dies of the set of memory dies and may output, to the host device, an indication of the memory die that identified the fault condition based on coupling the pin to the second resistor.

公开(公告)号：US20240404581A1

公开(公告)日：2024-12-05

申请号：US18667791

申请日：2024-05-17

Applicant: Micron Technology, Inc.

Inventor： Ameen D. Akel ,  Brent Keeth ,  James Brian Johnson ,  Chun-Yi Liu ,  Shivasankar Gunasekaran ,  Paul A. Laberge ,  Gregory A. King ,  Sai Krishna Mylavarapu ,  Su Wei Lim ,  Nathan A. Eckel ,  Lance P. Johnson ,  Nathan D. Henningson

IPC: G11C11/4093 ,  H01L23/00 ,  H01L25/065 ,  H01L25/18 ,  H10B80/00

Abstract: Methods, systems, and devices for interface techniques for stacked memory architectures are described. A semiconductor system, such as a memory system, may distribute memory access circuitry among multiple semiconductor dies of a stack. A first die of the system may include logic circuitry operable to configure a set of multiple first interface blocks of the first die. Each first interface block may include circuitry operable to communicate with one or more second interface blocks of one or more second dies of the system to access a respective set of one or more memory arrays of the one or more second dies. In some examples, the system may include a respective controller for each first interface block to support access operations via the first interface block. The system may also include non-volatile storage, one or more sensors, or a combination thereof to support various operations of the system.

公开(公告)号：US20240402909A1

公开(公告)日：2024-12-05

申请号：US18670074

申请日：2024-05-21

Applicant: Micron Technology, Inc.

Inventor： Nathan A. Eckel ,  Lance P. Johnson ,  Paul A. Laberge

IPC: G06F3/06

Abstract: Methods, systems, and devices for an interface layout for stacked memory architectures are described. A memory interface block may interface a plurality of memory dies to a host controller. The memory interface block may include an interface block coupled with multiple memory dies, which may be stacked on the memory interface block using through-silicon-vias. The memory interface block may include controllers, datapath blocks, and interface blocks associated with each memory die. As such, the memory interface block may perform functions such as queueing, ECC, and performing row repair and column repair procedures. In some examples, a layout for the memory interface block may include pairing controllers for at least two memory devices, such that a pair of controllers may share a command port to a pair of memory dies. Further, the memory interface block may include interfaces to the host controller that are different from the interface to each memory die.

公开(公告)号：US20240282400A1

公开(公告)日：2024-08-22

申请号：US18443948

申请日：2024-02-16

Applicant: Micron Technology, Inc.

Inventor： Scott E. Schaefer ,  Paul A. Laberge

IPC: G11C29/52

CPC classification number: G11C29/52

Abstract: Methods, systems, and devices for differential strobe fault indication are described. A memory device may be configured to indicate a fault using a read strobe signal. The read strobe signal may be a read data strobe (RDQS) signal, such as a true RDQS (RDQS_t) signal or a complement RDQS (RDQS_c) signal. In some examples, the memory device may indicate the fault based on a characteristic of the read strobe signal, such as a pattern of the read strobe signal, a voltage level of the read strobe signal, a difference between a first read strobe signal and a second read strobe signal, or any combination thereof. In some examples, a host device may identify a fault type (e.g., recoverable or unrecoverable) based on a fault signature associated with a given characteristic of the read strobe signal. The host device may perform recovery operations based on the fault type identified.