公开(公告)号：US11335563B2

公开(公告)日：2022-05-17

申请号：US16807002

申请日：2020-03-02

Applicant: Micron Technology, Inc.

Inventor： Baosuo Zhou ,  Mirzafer K. Abatchev ,  Ardavan Niroomand ,  Paul A. Morgan ,  Shuang Meng ,  Joseph Neil Greeley ,  Brian J. Coppa

IPC: H01L21/306 ,  H01L21/033 ,  H01L21/308 ,  H01L23/00

Abstract: A method for patterning a layer increases the density of features formed over an initial patterning layer using a series of self-aligned spacers. A layer to be etched is provided, then an initial sacrificial patterning layer, for example formed using optical lithography, is formed over the layer to be etched. Depending on the embodiment, the patterning layer may be trimmed, then a series of spacer layers formed and etched. The number of spacer layers and their target dimensions depends on the desired increase in feature density. An in-process semiconductor device and electronic system is also described.

公开(公告)号：US20160203993A1

公开(公告)日：2016-07-14

申请号：US15076474

申请日：2016-03-21

Applicant: Micron Technology, Inc.

Inventor： Baosuo Zhou ,  Mirzafer K. Abatchev ,  Ardavan Niroomand ,  Paul A. Morgan ,  Shuang Meng ,  Joseph Neil Greeley ,  Brian J. Coppa

IPC: H01L21/306

CPC classification number: H01L21/30625 ,  H01L21/0335 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/30604 ,  H01L21/3086 ,  H01L21/3088 ,  H01L23/564 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for patterning a layer increases the density of features formed over an initial patterning layer using a series of self-aligned spacers. A layer to be etched is provided, then an initial sacrificial patterning layer, for example formed using optical lithography, is formed over the layer to be etched. Depending on the embodiment, the patterning layer may be trimmed, then a series of spacer layers formed and etched. The number of spacer layers and their target dimensions depends on the desired increase in feature density. An in-process semiconductor device and electronic system is also described.

公开(公告)号：US20150021744A1

公开(公告)日：2015-01-22

申请号：US14507507

申请日：2014-10-06

Applicant: Micron Technology, Inc.

Inventor： Baosuo Zhou ,  Mirzafer K. Abatchev ,  Ardavan Niroomand ,  Paul A. Morgan ,  Shuang Meng ,  Joseph Neil Greely ,  Brian J. Coppa

IPC: H01L21/033 ,  H01L23/00

CPC classification number: H01L21/30625 ,  H01L21/0335 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/30604 ,  H01L21/3086 ,  H01L21/3088 ,  H01L23/564 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for patterning a layer increases the density of features formed over an initial patterning layer using a series of self-aligned spacers. A layer to be etched is provided, then an initial sacrificial patterning layer, for example formed using optical lithography, is formed over the layer to be etched. Depending on the embodiment, the patterning layer may be trimmed, then a series of spacer layers formed and etched. The number of spacer layers and their target dimensions depends on the desired increase in feature density. An in-process semiconductor device and electronic system is also described.

Abstract translation: 图案化层的方法使用一系列自对准间隔物增加在初始图案化层上形成的特征的密度。 提供待蚀刻的层，然后在待蚀刻的层上形成例如使用光学光刻形成的初始牺牲图案形成层。 根据实施例，图案化层可以被修整，然后形成并蚀刻一系列间隔层。 间隔层的数量及其目标尺寸取决于所需的特征密度增加。 还描述了一种过程中半导体器件和电子系统。

公开(公告)号：US20150001673A1

公开(公告)日：2015-01-01

申请号：US14324945

申请日：2014-07-07

Applicant: Micron Technology, Inc.

Inventor： Jiutao Li ,  Shuang Meng

IPC: C04B35/48 ,  H01L49/02

CPC classification number: H01L21/02181 ,  C04B35/48 ,  H01L21/02189 ,  H01L21/02332 ,  H01L21/31155 ,  H01L21/3143 ,  H01L21/31691 ,  H01L28/40

Abstract: A transition metal oxide dielectric material is doped with a non-metal in order to enhance the electrical properties of the metal oxide. In a preferred embodiment, a transition metal oxide is deposited over a bottom electrode and implanted with a dopant. In a preferred embodiment, the metal oxide is hafnium oxide or zirconium oxide and the dopant is nitrogen. The dopant can convert the crystal structure of the hafnium oxide or zirconium oxide to a tetragonal structure and increase the dielectric constant of the metal oxide.

Abstract translation: 过渡金属氧化物电介质材料掺杂有非金属，以增强金属氧化物的电性能。 在优选实施例中，过渡金属氧化物沉积在底部电极上并注入掺杂剂。 在优选的实施方案中，金属氧化物是氧化铪或氧化锆，掺杂剂是氮。 掺杂剂可将氧化铪或氧化锆的晶体结构转变为四方结构，并增加金属氧化物的介电常数。

公开(公告)号：US20180286693A1

公开(公告)日：2018-10-04

申请号：US15993568

申请日：2018-05-30

Applicant: Micron Technology, Inc.

Inventor： Baosuo Zhou ,  Mirzafer K. Abatchev ,  Ardavan Niroomand ,  Paul A. Morgan ,  Shuang Meng ,  Joseph Neil Greeley ,  Brian J. Coppa

IPC: H01L21/306 ,  H01L21/308 ,  H01L23/00 ,  H01L21/033

Abstract: A method for patterning a layer increases the density of features formed over an initial patterning layer using a series of self-aligned spacers. A layer to be etched is provided, then an initial sacrificial patterning layer, for example formed using optical lithography, is formed over the layer to be etched. Depending on the embodiment, the patterning layer may be trimmed, then a series of spacer layers formed and etched. The number of spacer layers and their target dimensions depends on the desired increase in feature density. An in-process semiconductor device and electronic system is also described.

公开(公告)号：US20220254644A1

公开(公告)日：2022-08-11

申请号：US17730478

申请日：2022-04-27

Applicant: Micron Technology, Inc.

Inventor： Baosuo Zhou ,  Mirzafer K. Abatchev ,  Ardavan Niroomand ,  Paul A. Morgan ,  Shuang Meng ,  Joseph Neil Greeley ,  Brian J. Coppa

IPC: H01L21/306 ,  H01L21/033 ,  H01L21/308 ,  H01L23/00

Abstract: A method for patterning a layer increases the density of features formed over an initial patterning layer using a series of self-aligned spacers. A layer to be etched is provided, then an initial sacrificial patterning layer, for example formed using optical lithography, is formed over the layer to be etched. Depending on the embodiment, the patterning layer may be trimmed, then a series of spacer layers formed and etched. The number of spacer layers and their target dimensions depends on the desired increase in feature density. An in-process semiconductor device and electronic system is also described.

公开(公告)号：US20170372913A1

公开(公告)日：2017-12-28

申请号：US15681066

申请日：2017-08-18

Applicant: Micron Technology, Inc.

Inventor： Baosuo Zhou ,  Mirzafer K. Abatchev ,  Ardavan Niroomand ,  Paul A. Morgan ,  Shuang Meng ,  Joseph Neil Greeley ,  Brian J. Coppa

IPC: H01L21/306 ,  H01L23/00 ,  H01L21/033 ,  H01L21/308

CPC classification number: H01L21/30625 ,  H01L21/0335 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/30604 ,  H01L21/3086 ,  H01L21/3088 ,  H01L23/564 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for patterning a layer increases the density of features formed over an initial patterning layer using a series of self-aligned spacers. A layer to be etched is provided, then an initial sacrificial patterning layer, for example formed using optical lithography, is formed over the layer to be etched. Depending on the embodiment, the patterning layer may be trimmed, then a series of spacer layers formed and etched. The number of spacer layers and their target dimensions depends on the desired increase in feature density. An in-process semiconductor device and electronic system is also described.

公开(公告)号：US09305782B2

公开(公告)日：2016-04-05

申请号：US14507507

申请日：2014-10-06

Applicant: Micron Technology, Inc.

Inventor： Baosuo Zhou ,  Mirzafer K. Abatchev ,  Ardavan Niroomand ,  Paul A. Morgan ,  Shuang Meng ,  Joseph Neil Greely ,  Brian J. Coppa

IPC: H01L21/033 ,  H01L23/00 ,  H01L21/308

CPC classification number: H01L21/30625 ,  H01L21/0335 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/30604 ,  H01L21/3086 ,  H01L21/3088 ,  H01L23/564 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for patterning a layer increases the density of features formed over an initial patterning layer using a series of self-aligned spacers. A layer to be etched is provided, then an initial sacrificial patterning layer, for example formed using optical lithography, is formed over the layer to be etched. Depending on the embodiment, the patterning layer may be trimmed, then a series of spacer layers formed and etched. The number of spacer layers and their target dimensions depends on the desired increase in feature density. An in-process semiconductor device and electronic system is also described.

Abstract translation: 图案化层的方法使用一系列自对准间隔物增加在初始图案化层上形成的特征的密度。 提供待蚀刻的层，然后在待蚀刻的层上形成例如使用光学光刻形成的初始牺牲图案形成层。 根据实施例，图案化层可以被修整，然后形成并蚀刻一系列间隔层。 间隔层的数量及其目标尺寸取决于所需的特征密度增加。 还描述了一种过程中半导体器件和电子系统。

公开(公告)号：US10607844B2

公开(公告)日：2020-03-31

申请号：US15993568

申请日：2018-05-30

Applicant: Micron Technology, Inc.

Inventor： Baosuo Zhou ,  Mirzafer K. Abatchev ,  Ardavan Niroomand ,  Paul A. Morgan ,  Shuang Meng ,  Joseph Neil Greeley ,  Brian J. Coppa

IPC: H01L21/306 ,  H01L21/033 ,  H01L21/308 ,  H01L23/00

Abstract: A method for patterning a layer increases the density of features formed over an initial patterning layer using a series of self-aligned spacers. A layer to be etched is provided, then an initial sacrificial patterning layer, for example formed using optical lithography, is formed over the layer to be etched. Depending on the embodiment, the patterning layer may be trimmed, then a series of spacer layers formed and etched. The number of spacer layers and their target dimensions depends on the desired increase in feature density. An in-process semiconductor device and electronic system is also described.

公开(公告)号：US10096483B2

公开(公告)日：2018-10-09

申请号：US15681066

申请日：2017-08-18

Applicant: Micron Technology, Inc.

Inventor： Baosuo Zhou ,  Mirzafer K. Abatchev ,  Ardavan Niroomand ,  Paul A. Morgan ,  Shuang Meng ,  Joseph Neil Greeley ,  Brian J. Coppa

IPC: H01L21/306 ,  H01L21/033 ,  H01L21/308 ,  H01L23/00

Abstract: A method for patterning a layer increases the density of features formed over an initial patterning layer using a series of self-aligned spacers. A layer to be etched is provided, then an initial sacrificial patterning layer, for example formed using optical lithography, is formed over the layer to be etched. Depending on the embodiment, the patterning layer may be trimmed, then a series of spacer layers formed and etched. The number of spacer layers and their target dimensions depends on the desired increase in feature density. An in-process semiconductor device and electronic system is also described.