公开(公告)号：US11335563B2

公开(公告)日：2022-05-17

申请号：US16807002

申请日：2020-03-02

Applicant: Micron Technology, Inc.

Inventor： Baosuo Zhou ,  Mirzafer K. Abatchev ,  Ardavan Niroomand ,  Paul A. Morgan ,  Shuang Meng ,  Joseph Neil Greeley ,  Brian J. Coppa

IPC: H01L21/306 ,  H01L21/033 ,  H01L21/308 ,  H01L23/00

Abstract: A method for patterning a layer increases the density of features formed over an initial patterning layer using a series of self-aligned spacers. A layer to be etched is provided, then an initial sacrificial patterning layer, for example formed using optical lithography, is formed over the layer to be etched. Depending on the embodiment, the patterning layer may be trimmed, then a series of spacer layers formed and etched. The number of spacer layers and their target dimensions depends on the desired increase in feature density. An in-process semiconductor device and electronic system is also described.

公开(公告)号：US20160203993A1

公开(公告)日：2016-07-14

申请号：US15076474

申请日：2016-03-21

Applicant: Micron Technology, Inc.

Inventor： Baosuo Zhou ,  Mirzafer K. Abatchev ,  Ardavan Niroomand ,  Paul A. Morgan ,  Shuang Meng ,  Joseph Neil Greeley ,  Brian J. Coppa

IPC: H01L21/306

CPC classification number: H01L21/30625 ,  H01L21/0335 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/30604 ,  H01L21/3086 ,  H01L21/3088 ,  H01L23/564 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for patterning a layer increases the density of features formed over an initial patterning layer using a series of self-aligned spacers. A layer to be etched is provided, then an initial sacrificial patterning layer, for example formed using optical lithography, is formed over the layer to be etched. Depending on the embodiment, the patterning layer may be trimmed, then a series of spacer layers formed and etched. The number of spacer layers and their target dimensions depends on the desired increase in feature density. An in-process semiconductor device and electronic system is also described.

公开(公告)号：US20150021744A1

公开(公告)日：2015-01-22

申请号：US14507507

申请日：2014-10-06

Applicant: Micron Technology, Inc.

Inventor： Baosuo Zhou ,  Mirzafer K. Abatchev ,  Ardavan Niroomand ,  Paul A. Morgan ,  Shuang Meng ,  Joseph Neil Greely ,  Brian J. Coppa

IPC: H01L21/033 ,  H01L23/00

CPC classification number: H01L21/30625 ,  H01L21/0335 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/30604 ,  H01L21/3086 ,  H01L21/3088 ,  H01L23/564 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for patterning a layer increases the density of features formed over an initial patterning layer using a series of self-aligned spacers. A layer to be etched is provided, then an initial sacrificial patterning layer, for example formed using optical lithography, is formed over the layer to be etched. Depending on the embodiment, the patterning layer may be trimmed, then a series of spacer layers formed and etched. The number of spacer layers and their target dimensions depends on the desired increase in feature density. An in-process semiconductor device and electronic system is also described.

Abstract translation: 图案化层的方法使用一系列自对准间隔物增加在初始图案化层上形成的特征的密度。 提供待蚀刻的层，然后在待蚀刻的层上形成例如使用光学光刻形成的初始牺牲图案形成层。 根据实施例，图案化层可以被修整，然后形成并蚀刻一系列间隔层。 间隔层的数量及其目标尺寸取决于所需的特征密度增加。 还描述了一种过程中半导体器件和电子系统。

公开(公告)号：US20130105937A1

公开(公告)日：2013-05-02

申请号：US13725915

申请日：2012-12-21

Applicant: Micron Technology, Inc.

Inventor： Ardavan Niroomand ,  Baosuo Zhou ,  Ramakanth Alapati

IPC: H01L27/04

CPC classification number: H01L27/04 ,  H01L21/0338 ,  H01L21/3088 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for fabricating a semiconductor device comprises patterning a layer of photoresist material to form a plurality of mandrels. The method further comprises depositing an oxide material over the plurality of mandrels by an atomic layer deposition (ALD) process. The method further comprises anisotropically etching the oxide material from exposed horizontal surfaces. The method further comprises selectively etching photoresist material.

Abstract translation: 一种用于制造半导体器件的方法包括对一层光致抗蚀剂材料进行构图以形成多个心轴。 该方法还包括通过原子层沉积（ALD）工艺在多个心轴上沉积氧化物材料。 该方法还包括从暴露的水平表面各向异性地蚀刻氧化物材料。 该方法还包括选择性地蚀刻光刻胶材料。

公开(公告)号：US20180286693A1

公开(公告)日：2018-10-04

申请号：US15993568

申请日：2018-05-30

Applicant: Micron Technology, Inc.

Inventor： Baosuo Zhou ,  Mirzafer K. Abatchev ,  Ardavan Niroomand ,  Paul A. Morgan ,  Shuang Meng ,  Joseph Neil Greeley ,  Brian J. Coppa

IPC: H01L21/306 ,  H01L21/308 ,  H01L23/00 ,  H01L21/033

Abstract: A method for patterning a layer increases the density of features formed over an initial patterning layer using a series of self-aligned spacers. A layer to be etched is provided, then an initial sacrificial patterning layer, for example formed using optical lithography, is formed over the layer to be etched. Depending on the embodiment, the patterning layer may be trimmed, then a series of spacer layers formed and etched. The number of spacer layers and their target dimensions depends on the desired increase in feature density. An in-process semiconductor device and electronic system is also described.

公开(公告)号：US10607844B2

公开(公告)日：2020-03-31

申请号：US15993568

申请日：2018-05-30

Applicant: Micron Technology, Inc.

Inventor： Baosuo Zhou ,  Mirzafer K. Abatchev ,  Ardavan Niroomand ,  Paul A. Morgan ,  Shuang Meng ,  Joseph Neil Greeley ,  Brian J. Coppa

IPC: H01L21/306 ,  H01L21/033 ,  H01L21/308 ,  H01L23/00

Abstract: A method for patterning a layer increases the density of features formed over an initial patterning layer using a series of self-aligned spacers. A layer to be etched is provided, then an initial sacrificial patterning layer, for example formed using optical lithography, is formed over the layer to be etched. Depending on the embodiment, the patterning layer may be trimmed, then a series of spacer layers formed and etched. The number of spacer layers and their target dimensions depends on the desired increase in feature density. An in-process semiconductor device and electronic system is also described.

公开(公告)号：US10096483B2

公开(公告)日：2018-10-09

申请号：US15681066

申请日：2017-08-18

Applicant: Micron Technology, Inc.

Inventor： Baosuo Zhou ,  Mirzafer K. Abatchev ,  Ardavan Niroomand ,  Paul A. Morgan ,  Shuang Meng ,  Joseph Neil Greeley ,  Brian J. Coppa

IPC: H01L21/306 ,  H01L21/033 ,  H01L21/308 ,  H01L23/00

Abstract: A method for patterning a layer increases the density of features formed over an initial patterning layer using a series of self-aligned spacers. A layer to be etched is provided, then an initial sacrificial patterning layer, for example formed using optical lithography, is formed over the layer to be etched. Depending on the embodiment, the patterning layer may be trimmed, then a series of spacer layers formed and etched. The number of spacer layers and their target dimensions depends on the desired increase in feature density. An in-process semiconductor device and electronic system is also described.

公开(公告)号：US09761457B2

公开(公告)日：2017-09-12

申请号：US15076474

申请日：2016-03-21

Applicant: Micron Technology, Inc.

Inventor： Baosuo Zhou ,  Mirzafer K. Abatchev ,  Ardavan Niroomand ,  Paul A. Morgan ,  Shuang Meng ,  Joseph Neil Greeley ,  Brian J. Coppa

IPC: H01L21/306 ,  H01L21/033 ,  H01L21/308 ,  H01L23/00

CPC classification number: H01L21/30625 ,  H01L21/0335 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/30604 ,  H01L21/3086 ,  H01L21/3088 ,  H01L23/564 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for patterning a layer increases the density of features formed over an initial patterning layer using a series of self-aligned spacers. A layer to be etched is provided, then an initial sacrificial patterning layer, for example formed using optical lithography, is formed over the layer to be etched. Depending on the embodiment, the patterning layer may be trimmed, then a series of spacer layers formed and etched. The number of spacer layers and their target dimensions depends on the desired increase in feature density. An in-process semiconductor device and electronic system is also described.

公开(公告)号：US08871648B2

公开(公告)日：2014-10-28

申请号：US13690266

申请日：2012-11-30

Applicant: Micron Technology, Inc.

Inventor： Baosuo Zhou ,  Gurtej S. Sandhu ,  Ardavan Niroomand

IPC: H01L21/311 ,  H01L21/033 ,  H01L21/768

CPC classification number: H01L21/76885 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/76816

Abstract: In one or more embodiments, a method is provided for forming an integrated circuit with a pattern of isolated features having a final density of isolated features that is greater than a starting density of isolated features in an integrated circuit by a multiple of two or more. The method can include forming a pattern of pillars having a density X, and forming a pattern of holes amongst the pillars, the holes having a density at least X. The pillars can be selectively removed to form a pattern of holes having a density at least 2X. In some embodiments, plugs can be formed in the pattern of holes, such as by epitaxial deposition on the substrate, in order to provide a pattern of pillars having a density 2X. In other embodiments, the pattern of holes can be transferred to the substrate by etching.

Abstract translation: 在一个或多个实施例中，提供了一种用于形成具有隔离特征图案的集成电路的方法，其具有比集成电路中的隔离特征的起始密度多两倍或更多的孤立特征的最终密度。 该方法可以包括形成具有密度X的柱状图案，并且在柱之间形成孔的图案，孔的密度至少为X.可以选择性地去除柱，以形成至少具有密度的孔的图案 2X。 在一些实施例中，插塞可以以空穴的图案形成，例如通过外延沉积在基板上，以便提供具有密度2X的柱状图案。 在其他实施例中，孔的图案可以通过蚀刻转移到衬底。

公开(公告)号：US20220254644A1

公开(公告)日：2022-08-11

申请号：US17730478

申请日：2022-04-27

Applicant: Micron Technology, Inc.

Inventor： Baosuo Zhou ,  Mirzafer K. Abatchev ,  Ardavan Niroomand ,  Paul A. Morgan ,  Shuang Meng ,  Joseph Neil Greeley ,  Brian J. Coppa

IPC: H01L21/306 ,  H01L21/033 ,  H01L21/308 ,  H01L23/00

Abstract: A method for patterning a layer increases the density of features formed over an initial patterning layer using a series of self-aligned spacers. A layer to be etched is provided, then an initial sacrificial patterning layer, for example formed using optical lithography, is formed over the layer to be etched. Depending on the embodiment, the patterning layer may be trimmed, then a series of spacer layers formed and etched. The number of spacer layers and their target dimensions depends on the desired increase in feature density. An in-process semiconductor device and electronic system is also described.