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    Methods of forming capacitors
    5.
    发明授权
    Methods of forming capacitors 有权

    公开(公告)号：US09159780B2

    公开(公告)日：2015-10-13

    申请号：US14596429

    申请日：2015-01-14

    Applicant: Micron Technology, Inc.

    Inventor： Joseph Neil Greeley ,  Prashant Raghu ,  Niraj B. Rana

    IPC: H01L21/02 ,  H01L49/02 ,  H01L21/3213 ,  H01L27/108

    CPC classification number: H01L28/92 ,  H01L21/32133 ,  H01L27/108 ,  H01L27/10852 ,  H01L27/10861 ,  H01L28/90

    Abstract: A method of forming capacitors includes forming support material over a substrate. A first capacitor electrode is formed within individual openings in the support material. A first etching is conducted only partially into the support material using a liquid etching fluid to expose an elevationally outer portion of sidewalls of individual of the first capacitor electrodes. A second etching is conducted into the support material using a dry etching fluid to expose an elevationally inner portion of the sidewalls of the individual first capacitor electrodes. A capacitor dielectric is formed over the outer and inner portions of the sidewalls of the first capacitor electrodes. A second capacitor electrode is formed over the capacitor dielectric.

    Multi-Material Structures, Semiconductor Constructions and Methods of Forming Capacitors
    6.
    发明申请
    Multi-Material Structures, Semiconductor Constructions and Methods of Forming Capacitors 有权
    多材料结构，半导体结构和形成电容器的方法

    公开(公告)号：US20150054127A1

    公开(公告)日：2015-02-26

    申请号：US14501423

    申请日：2014-09-30

    Applicant: Micron Technology, Inc.

    Inventor： Joseph Neil Greeley ,  Duane M. Goodner ,  Vishwanath Bhat ,  Vassil N. Antonov ,  Prashant Raghu

    IPC: H01L49/02

    CPC classification number: H01L28/75 ,  B82Y30/00 ,  H01L27/10808 ,  H01L27/10852 ,  H01L28/65 ,  H01L28/90 ,  Y10S977/932 ,  Y10T428/265

    Abstract: Some embodiments include a method of forming a capacitor. An opening is formed through a silicon-containing mass to a base, and sidewalls of the opening are lined with protective material. A first capacitor electrode is formed within the opening and has sidewalls along the protective material. At least some of the silicon-containing mass is removed with an etch. The protective material protects the first capacitor electrode from being removed by the etch. A second capacitor electrode is formed along the sidewalls of the first capacitor electrode, and is spaced from the first capacitor electrode by capacitor dielectric. Some embodiments include multi-material structures having one or more of aluminum nitride, molybdenum nitride, niobium nitride, niobium oxide, silicon dioxide, tantalum nitride and tantalum oxide. Some embodiments include semiconductor constructions.

    Abstract translation: 一些实施例包括形成电容器的方法。 通过含硅物质向基底形成开口，并且开口的侧壁衬有保护材料。 第一电容器电极形成在开口内并具有保护材料的侧壁。 用蚀刻去除至少一些含硅物质。 保护材料保护第一电容器电极不被蚀刻除去。 沿着第一电容器电极的侧壁形成第二电容器电极，并且通过电容器电介质与第一电容器电极间隔开。 一些实施例包括具有氮化铝，氮化钼，氮化铌，氧化铌，二氧化硅，氮化钽和氧化钽中的一种或多种的多材料结构。 一些实施例包括半导体结构。

    Methods of forming an array of elevationally-extending strings of memory cells individually comprising a programmable charge-storage transistor
    7.
    发明授权
    Methods of forming an array of elevationally-extending strings of memory cells individually comprising a programmable charge-storage transistor 有权

    公开(公告)号：US10580782B2

    公开(公告)日：2020-03-03

    申请号：US15903254

    申请日：2018-02-23

    Applicant: Micron Technology, Inc.

    Inventor： Wei Yeeng Ng ,  Ian Laboriante ,  Joseph Neil Greeley ,  Tom J. John ,  Ho Yee Hui

    IPC: H01L27/115 ,  H01L27/11556 ,  H01L27/11524 ,  H01L27/1157 ,  H01L27/11582 ,  H01L23/522 ,  H01L21/3213 ,  H01L21/311 ,  H01L21/768 ,  H01L21/28

    Abstract: A method of forming an array of elevationally-extending strings of memory cells comprises forming a stack comprising alternating insulative tiers and wordline tiers. A select gate tier is above an upper of the insulative tiers. Channel openings extend through the alternating tiers and the select gate tier. Charge-storage material is formed within the channel openings elevationally along the alternating tiers and the select gate tier. Sacrificial material is formed within the channel openings laterally over the charge-storage material that is laterally over the select gate tier and that is laterally over the alternating tiers. Elevationally-outer portions of each of the charge-storage material and the sacrificial material that are within the channel openings are etched. After such etching, the sacrificial material is removed from the channel openings. After such removing, insulative charge-passage material then channel material are formed within the channel openings laterally over the charge-storage material that is laterally over the wordline tiers. The wordline tiers are formed to comprise control-gate material having terminal ends corresponding to control-gate regions of individual memory cells and to have a charge-blocking region of the individual memory cells laterally between the charge-storage material and individual of the control-gate regions.

    Multi-material structures and capacitor-containing semiconductor constructions
    9.
    发明授权
    Multi-material structures and capacitor-containing semiconductor constructions 有权
    多材料结构和含电容器的半导体结构

    公开(公告)号：US09236427B2

    公开(公告)日：2016-01-12

    申请号：US14501423

    申请日：2014-09-30

    Applicant: Micron Technology, Inc.

    Inventor： Joseph Neil Greeley ,  Duane M. Goodner ,  Vishwanath Bhat ,  Vassil N. Antonov ,  Prashant Raghu

    IPC: H01L27/108 ,  H01L29/94 ,  H01L49/02 ,  B82Y30/00

    CPC classification number: H01L28/75 ,  B82Y30/00 ,  H01L27/10808 ,  H01L27/10852 ,  H01L28/65 ,  H01L28/90 ,  Y10S977/932 ,  Y10T428/265

    Abstract: Some embodiments include a method of forming a capacitor. An opening is formed through a silicon-containing mass to a base, and sidewalls of the opening are lined with protective material. A first capacitor electrode is formed within the opening and has sidewalls along the protective material. At least some of the silicon-containing mass is removed with an etch. The protective material protects the first capacitor electrode from being removed by the etch. A second capacitor electrode is formed along the sidewalls of the first capacitor electrode, and is spaced from the first capacitor electrode by capacitor dielectric. Some embodiments include multi-material structures having one or more of aluminum nitride, molybdenum nitride, niobium nitride, niobium oxide, silicon dioxide, tantalum nitride and tantalum oxide. Some embodiments include semiconductor constructions.

    Abstract translation: 一些实施例包括形成电容器的方法。 通过含硅物质向基底形成开口，并且开口的侧壁衬有保护材料。 第一电容器电极形成在开口内并具有保护材料的侧壁。 用蚀刻去除至少一些含硅物质。 保护材料保护第一电容器电极不被蚀刻除去。 沿着第一电容器电极的侧壁形成第二电容器电极，并且通过电容器电介质与第一电容器电极间隔开。 一些实施例包括具有氮化铝，氮化钼，氮化铌，氧化铌，二氧化硅，氮化钽和氧化钽中的一种或多种的多材料结构。 一些实施例包括半导体结构。

    Methods of Removing Particles from Over Semiconductor Substrates
    10.
    发明申请
    Methods of Removing Particles from Over Semiconductor Substrates 审中-公开
    从半导体衬底去除颗粒的方法

    公开(公告)号：US20150128992A1

    公开(公告)日：2015-05-14

    申请号：US14605218

    申请日：2015-01-26

    Applicant: Micron Technology, Inc.

    Inventor： Joseph Neil Greeley ,  Dan Millward ,  Wayne Huang

    IPC: B08B3/10 ,  H01L21/02 ,  B08B3/12

    CPC classification number: B08B3/10 ,  B08B3/12 ,  H01L21/02041 ,  H01L21/02057 ,  H01L21/67057

    Abstract: Some embodiments include methods of removing particles from over surfaces of semiconductor substrates. Liquid may be flowed across the surfaces and the particles. While the liquid is flowing, electrophoresis and/or electroosmosis may be utilized to enhance transport of the particles from the surfaces and into the liquid. In some embodiments, temperature, pH and/or ionic strength within the liquid may be altered to assist in the removal of the particles from over the surfaces of the substrates.

    Abstract translation: 一些实施例包括从半导体衬底的过表面去除颗粒的方法。 液体可以流过表面和颗粒。 当液体流动时，可以使用电泳和/或电渗来增强颗粒从表面和液体中的转运。 在一些实施方案中，可以改变液体内的温度，pH和/或离子强度，以有助于从基底表面上除去颗粒。

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