公开(公告)号：US11995338B2

公开(公告)日：2024-05-28

申请号：US17745779

申请日：2022-05-16

申请人： MICRON TECHNOLOGY, INC.

发明人： Yang Zhang

IPC分类号： G06F3/06

CPC分类号： G06F3/0653 ,  G06F3/0604 ,  G06F3/064 ,  G06F3/0652 ,  G06F3/0679

摘要： A system includes a memory device having a plurality of data blocks and a processing device, the processing device to perform operations identifying an erase operation being performed on a first portion of a plurality of data blocks. The operations further include determining a first rate of performance of the erase operation being performed on the first portion of the plurality of data blocks, identifying a write operation being performed on a second portion of the plurality of data blocks, and determining a second rate of performance of the write operation being performed on the second portion of the plurality of data blocks. The operations further include determining whether the second rate of performance corresponds to the first rate of performance and responsive to the second rate of performance not corresponding to the first rate of performance, adjusting the second rate of performance.

公开(公告)号：US20220276801A1

公开(公告)日：2022-09-01

申请号：US17745779

申请日：2022-05-16

申请人： MICRON TECHNOLOGY, INC.

发明人： Yang Zhang

IPC分类号： G06F3/06

摘要： A system includes a memory device having a plurality of data blocks and a processing device, the processing device to perform operations identifying an erase operation being performed on a first portion of a plurality of data blocks. The operations further include determining a first rate of performance of the erase operation being performed on the first portion of the plurality of data blocks, identifying a write operation being performed on a second portion of the plurality of data blocks, and determining a second rate of performance of the write operation being performed on the second portion of the plurality of data blocks. The operations further include determining whether the second rate of performance corresponds to the first rate of performance and responsive to the second rate of performance not corresponding to the first rate of performance, adjusting the second rate of performance.

公开(公告)号：US20210072926A1

公开(公告)日：2021-03-11

申请号：US17100334

申请日：2020-11-20

申请人： Micron Technology, Inc.

发明人： Jiangang Wu ,  Sampath K. Ratnam ,  Yang Zhang ,  Guang Chang Ye ,  Kishore Kumar Muchherla ,  Hong Lu ,  Karl D. Schuh ,  Vamsi Pavan Rayaprolu

IPC分类号： G06F3/06

摘要： A program operation is executed on a memory sub-system. In response to receiving a request to execute a read operation, executing a first program suspend operation to suspend the program operation. In response to a completion of the read operation, a program resume operation is executed to resume execution of the program operation. A delay period is established following execution of the program resume operation during which execution of the program operation is completed. A second program suspend operation is executed following the delay period.

公开(公告)号：US11688475B2

公开(公告)日：2023-06-27

申请号：US17241015

申请日：2021-04-26

申请人： MICRON TECHNOLOGY, INC.

发明人： Yang Zhang

IPC分类号： G11C7/00 ,  G11C16/34 ,  G11C16/08 ,  G11C16/10 ,  G11C16/26 ,  G11C29/42

CPC分类号： G11C16/3459 ,  G11C16/08 ,  G11C16/10 ,  G11C16/26 ,  G11C16/3418 ,  G11C29/42

摘要： Data from a first memory cell of a plurality of memory cells is read, and it is determined whether the data stored at the first memory cell comprises an error. Upon determining that the data stored at the first memory cell comprises the error, it is determined whether an error correction operation on the data stored at the first memory cell is successful. Responsive to determining that the error correction operation on the data stored at the first memory cell is unsuccessful, a second memory cell of the plurality of memory cells is identified and a two-pass programming operation is performed on the second memory cell instead of the first memory cell.

公开(公告)号：US10991440B2

公开(公告)日：2021-04-27

申请号：US16636309

申请日：2018-03-07

申请人： MICRON TECHNOLOGY, INC.

发明人： Yang Zhang

IPC分类号： G11C16/34 ,  G11C16/10 ,  G11C16/26 ,  G11C16/08 ,  G11C29/42

摘要： Data from a first portion of a memory cell of a plurality of memory cells is read. A first programming pass is performed on another memory cell of the plurality of memory cells by providing new data to the another memory cell. A second programming pass is performed on the memory cell by providing additional data to the first portion of the memory cell based on the reading of the first portion of the memory cell. The first programming pass and the second programming pass correspond to a two-pass programming operation associated with the plurality of memory cells.

公开(公告)号：US11507317B2

公开(公告)日：2022-11-22

申请号：US17100334

申请日：2020-11-20

申请人： Micron Technology, Inc.

发明人： Jiangang Wu ,  Sampath K. Ratnam ,  Yang Zhang ,  Guang Chang Ye ,  Kishore Kumar Muchherla ,  Hong Lu ,  Karl D. Schuh ,  Vamsi Pavan Rayaprolu

IPC分类号： G06F3/06

摘要： A program operation is executed on a memory sub-system. In response to receiving a request to execute a read operation, executing a first program suspend operation to suspend the program operation. In response to a completion of the read operation, a program resume operation is executed to resume execution of the program operation. A delay period is established following execution of the program resume operation during which execution of the program operation is completed. A second program suspend operation is executed following the delay period.

公开(公告)号：US11334278B2

公开(公告)日：2022-05-17

申请号：US16636303

申请日：2018-03-01

申请人： MICRON TECHNOLOGY, INC.

发明人： Yang Zhang

IPC分类号： G06F3/06

摘要： A first operation is performed on a first portion of a plurality of data blocks. A request is received to perform a second operation associated with the plurality of data blocks. A rate of performance of the first operation on the first portion of the plurality of data blocks is determined. The second program operation is performed on a second portion of the plurality of data blocks based on the rate of performance of the first operation on the first portion of the plurality of data blocks.

公开(公告)号：US20200285416A1

公开(公告)日：2020-09-10

申请号：US16294416

申请日：2019-03-06

申请人： Micron Technology, Inc.

发明人： Jiangang Wu ,  Sampath K. Ratnam ,  Yang Zhang ,  Guang Chang Ye ,  Kishore Kumar Muchherla ,  Hong Lu ,  Karl D. Schuh ,  Vamsi Pavan Rayaprolu

IPC分类号： G06F3/06

摘要： A program operation is executed on a memory sub-system. During execution of the program operation, a request to execute a read operation on the memory sub-system is received. In response to receiving the request, a program suspend operation to suspend the program operation is executed. The read operation is executed on the memory sub-system in response to a completion of the program suspend operation. In response to completion of the read operation, a program resume operation is executed. A program suspend delay period is established following execution of the program resume operation during which a subsequent read operation is stored in a queue.