公开(公告)号：US20240170090A1

公开(公告)日：2024-05-23

申请号：US18492252

申请日：2023-10-23

Applicant: Micron Technology, Inc.

Inventor： Peng ZHANG ,  Lei LIN ,  Zhongguang XU ,  Li-Te CHANG ,  Zhengang CHEN ,  Murong LANG ,  Zhenming ZHOU

IPC: G11C29/52 ,  G11C16/10 ,  G11C16/26

CPC classification number: G11C29/52 ,  G11C16/102 ,  G11C16/26

Abstract: In some implementations, a memory device may determine that a power loss has occurred. The memory device may determine a last written page (LWP) location associated with an LWP of a block of a memory of the memory device. The memory device may determine one of: a word line group (WLG) associated with the LWP location and at least one WLG-dependent offset associated with the WLG, or a partial block (PB) fill ratio associated with the LWP location and at least one PB-fill-ratio-dependent offset associated with the PB fill ratio. The memory device may perform a power loss error detection procedure based on one of the at least one WLG-dependent offset or the at least one PB-fill-ratio offset by applying the one of the at least one WLG-dependent offset or the at least one PB-fill-ratio offset to at least one read reference voltage.

公开(公告)号：US20210026562A1

公开(公告)日：2021-01-28

申请号：US16523851

申请日：2019-07-26

Applicant: Micron Technology, Inc.

Inventor： Zhengang CHEN ,  Tingjun Xie

IPC: G06F3/06 ,  G06F16/245 ,  G11C16/26 ,  G11C16/10

Abstract: A system includes a memory component; and a processing device, operatively coupled with the memory component. The processing device is to receive a request to perform a read operation on data stored at a physical address of the memory component and determine whether the data satisfies a threshold criterion pertaining to when the data was written to the physical address. In response to the data satisfying the threshold criterion, the processing device is to perform the read operation on the data stored at the physical address using a first read voltage level, and in response to the data not satisfying the threshold criterion, perform the read operation on the data stored at the physical address using a second read voltage level.

公开(公告)号：US20240168847A1

公开(公告)日：2024-05-23

申请号：US18507805

申请日：2023-11-13

Applicant: Micron Technology, Inc.

Inventor： Mustafa N. KAYNAK ,  Eyal EN GAD ,  Zhengang CHEN ,  Sivagnanam PARTHASARATHY ,  Phong Sy NGUYEN ,  Dung V. NGUYEN

IPC: G06F11/10 ,  G06F11/07

CPC classification number: G06F11/1068 ,  G06F11/076 ,  G06F11/1016

Abstract: A method includes performing a read operation of a first codeword including first hard data and generating an error vector using a reliability metric of the first hard data. The first hard data and error vector are stored in first and second portions of memory. A first corrected codeword is returned that combines the error vector and the hard data from the first and second portions of memory. A read operation of a second codeword is performed, including second hard data and soft information. The hard data and soft information are stored in the first and second portions of memory. A bit of second hard data is flipped responsive to comparing a reliability metric of the bit of the second hard data to a bit flipping threshold, wherein flipping the bit includes updating the second hard data. The updated second codeword is returned resulting from reading the portions of memory.