公开(公告)号：US20230393750A1

公开(公告)日：2023-12-07

申请号：US18049973

申请日：2022-10-26

申请人： Micron Technology, Inc.

发明人： Ying Huang ,  Mark Ish

IPC分类号： G06F3/06

CPC分类号： G06F3/0613 ,  G06F3/0611 ,  G06F3/0659 ,  G06F3/0679

摘要： Methods, apparatuses and systems related to response completion pacing for latency control are described. The apparatus may utilize response completion pacing to dynamically control timing of output communications to the host. In some embodiments, the memory device can include a ready response queue that temporarily stores the data retrieved from a backend portion or a storage portion of the memory device. The apparatus can include logic coupled to the ready response queue and configured to communicate/send the data in the ready response queue according to a cadence period. In some embodiments, the logic can further dynamically adjust a storage capacity of the ready response queue and/or the cadence period.

公开(公告)号：US11782643B2

公开(公告)日：2023-10-10

申请号：US17393234

申请日：2021-08-03

申请人： Micron Technology, Inc.

发明人： Sanjay Subbarao ,  Mark Ish

IPC分类号： G06F3/06

CPC分类号： G06F3/0659 ,  G06F3/061 ,  G06F3/0653 ,  G06F3/0679

摘要： A memory sub-system configured to partially execute write commands from a host system to optimize performance. After receiving a write command from a host system, the memory sub-system can identify, based on a media physical layout, a preferred input/output size for the execution of the write command. The memory sub-system can execute the write command according to the preferred input/output size, configure a response for the write command to identify the second input/output size, and transmit the response identifying the second input/output size to the host system. The host system is configured to generate a subsequent write command to write at least the data that is initially identified in the write command that has been executed but not been included in the execution of the write command performed according to the preferred input/output size.

公开(公告)号：US11556258B1

公开(公告)日：2023-01-17

申请号：US17379118

申请日：2021-07-19

申请人： Micron Technology, Inc.

发明人： Ying Huang ,  Mark Ish

IPC分类号： G06F3/06 ,  G06F12/02

摘要： A processing device in a memory system identifies, while the memory device is in a first state condition, a plurality of workload conditions associated with the memory device, wherein the plurality of workload conditions comprise data reflecting a performance condition of the memory device. The processing device determines, while the memory device is in the first state condition, a host rate of a host system write performance for the memory device based on one or more workload conditions of the plurality of workload conditions. The processing device determines that one or more workload conditions of the plurality of workload conditions satisfies a first threshold criterion. Responsive to determining that the one or more workload conditions of the plurality of workload conditions satisfies the first threshold criterion, the processing device detects a change in a condition of the memory device from the first state to a second state. The processing device determines, while the memory device is in the second state condition, an adjusted host rate based on the host rate and a calculated adjustment value. The processing device uses the adjusted host rate to determine a credit consuming rate for a host write operation for the memory device.

公开(公告)号：US11513959B2

公开(公告)日：2022-11-29

申请号：US17185059

申请日：2021-02-25

申请人： Micron Technology, Inc.

发明人： Horia C. Simionescu ,  Lyle E. Adams ,  Yongcai Xu ,  Mark Ish

IPC分类号： G06F12/08 ,  G06F12/0855

摘要： A request to read data from a location associated with a memory component is received. The request is assigned a first tag, the first tag having a first identifier of a first buffer to store data read from the location. The request to read data is determined to collide with an earlier request to write data to the location. The earlier request is assigned a second tag, the second tag having a second identifier of a second buffer to store data to write to the location. An attempt to lock the second tag and the second buffer for the request to read data is made. The request to read data is fulfilled from the second buffer in response to a successful attempt to lock the second tag and the second buffer.

公开(公告)号：US20220237078A1

公开(公告)日：2022-07-28

申请号：US17160194

申请日：2021-01-27

申请人： Micron Technology, Inc.

发明人： Gerald L. Cadloni ,  Mark Ish ,  James P. Crowley

IPC分类号： G06F11/10 ,  G06F11/07 ,  G06F11/30 ,  G06F12/02 ,  G06F12/0882 ,  G06F12/1081

摘要： A total read counter, a plurality of die read counters, and a plurality of block read counters are maintained. Each die read counter is associated with a respective die of a memory device. A value of a block read counter and a value of a die read counter are determined for a specified block. Based on the value of the block read counter, the value of the die read counter, and the value of the total read counter, an estimated number of read events associated with the specified block of the memory device is determined. Responsive to determining that the estimated number of read events satisfies a predefined criterion, a media management operation of one or more pages associated with the specified block is performed.

公开(公告)号：US11347434B2

公开(公告)日：2022-05-31

申请号：US16854282

申请日：2020-04-21

申请人： Micron Technology, Inc.

发明人： Mark Ish

IPC分类号： G06F3/06 ,  G11C16/26 ,  G11C16/04

摘要： An example memory sub-system includes a memory device and a processing device, operatively coupled to the memory device. The processing device is configured to receive a read command specifying an identifier of a logical block and a page number; translate the identifier of the logical block into a physical address of a physical block stored on the memory device, wherein the physical address comprises an identifier of a memory device die; identify, based on block family metadata associated with the memory device, a block family associated with the physical block and the page number; determine a threshold voltage offset associated with the block family and the memory device die; compute a modified threshold voltage by applying the threshold voltage offset to a base read level voltage associated with the memory device die; and read, using the modified threshold voltage, data from a physical page identified by the page number within the physical block.

公开(公告)号：US20220129376A1

公开(公告)日：2022-04-28

申请号：US17572477

申请日：2022-01-10

申请人： Micron Technology, Inc.

发明人： Sanjay Subbarao ,  Johnny A. Lam ,  John E. Maroney ,  Mark Ish

IPC分类号： G06F12/02 ,  G06F12/0873 ,  G06F9/355 ,  G06F12/0882

摘要： A system includes integrated circuit (IC) dies having memory cells and a processing device, which is to perform operations including generating a number of zone map entries for zones of a logical block address (LBA) space that are sequentially mapped to physical address space of the plurality of IC dies, wherein each zone map entry corresponds to a respective data group that has been sequentially written to one or more IC dies; and generating a die identifier and a block identifier for each data block of multiple data blocks of the respective data group, wherein each data block corresponds to a media block of the plurality of IC dies.

公开(公告)号：US11204721B2

公开(公告)日：2021-12-21

申请号：US16865247

申请日：2020-05-01

申请人： Micron Technology, Inc.

发明人： Sanjay Subbarao ,  Mark Ish

IPC分类号： G06F3/06 ,  G06F12/1009 ,  G11C16/04

摘要： A memory sub-system configured to dynamically determine input/output sizes of write commands based on a media physical layout of a memory sub-system. The memory sub-system can identify, dynamically in response to write commands being selected for execution in media units of the memory sub-system, a portion of a media layout that maps from logical addresses identified by the write commands in the logical address space to physical addresses of memory units in the media units. Based on the media layout, an input/output size for a next write command is identified and transmitted to the host system in a response. The host system generates the next write command and configures the amount of data to be written through the next write command based on the input/output size identified in the response.

公开(公告)号：US20210382658A1

公开(公告)日：2021-12-09

申请号：US17393234

申请日：2021-08-03

申请人： Micron Technology, Inc.

发明人： Sanjay Subbarao ,  Mark Ish

IPC分类号： G06F3/06

摘要： A memory sub-system configured to partially execute write commands from a host system to optimize performance. After receiving a write command from a host system, the memory sub-system can identify, based on a media physical layout, a preferred input/output size for the execution of the write command. The memory sub-system can execute the write command according to the preferred input/output size, configure a response for the write command to identify the second input/output size, and transmit the response identifying the second input/output size to the host system. The host system is configured to generate a subsequent write command to write at least the data that is initially identified in the write command that has been executed but not been included in the execution of the write command performed according to the preferred input/output size.

公开(公告)号：US20210303470A1

公开(公告)日：2021-09-30

申请号：US16833306

申请日：2020-03-27

申请人： Micron Technology, Inc.

发明人： Scheheresade Virani ,  Aleksei Vlasov ,  Mark Ish

IPC分类号： G06F12/0853 ,  G06F12/123 ,  G06F9/50 ,  G06F11/30

摘要： Methods, systems, and devices for sequential prefetching through a linking array are described. A prefetch manager can detect that a set of tags occupying a queue of a memory sub-system corresponds to a single read descriptor indicating a sequential read pattern. The prefetch manager can determine that a number of the set of tags occupying the queue is below a queue threshold and store data associated with at least one tag of the set of tags in an internal performance memory of the memory sub-system based on the detecting and the determining. In such cases, the prefetch manager can prefetch data from a memory manager and store in the internal performance memory.