公开(公告)号：US20230021072A1

公开(公告)日：2023-01-19

申请号：US17947038

申请日：2022-09-16

Applicant: Micron Technology, Inc.

Inventor： Raju Ahmed ,  Radhakrishna Kotti ,  David A. Kewley ,  Dave Pratt

IPC: H01L23/528 ,  H01L23/522

Abstract: Some embodiments include an integrated assembly having a base which includes first circuitry. Memory decks are over the base. Each of the memory decks has a sense/access line coupled with the first circuitry. The memory decks and base are vertically spaced from one another by gaps. The gaps alternate in a vertical direction between first gaps and second gaps. Overlapping conductive paths extend from the sense/access lines to the first circuitry. The conductive paths include first conductive interconnects within the first gaps and second conductive interconnects within the second gaps. The first and second conductive interconnects are laterally offset relative to one another.

公开(公告)号：US20220013449A1

公开(公告)日：2022-01-13

申请号：US16925767

申请日：2020-07-10

Applicant: Micron Technology, Inc.

Inventor： Raju Ahmed ,  Radhakrishna Kotti ,  David A. Kewley ,  Dave Pratt

IPC: H01L23/528 ,  H01L23/522

Abstract: Some embodiments include an integrated assembly having a base which includes first circuitry. Memory decks are over the base. Each of the memory decks has a sense/access line coupled with the first circuitry. The memory decks and base are vertically spaced from one another by gaps. The gaps alternate in a vertical direction between first gaps and second gaps. Overlapping conductive paths extend from the sense/access lines to the first circuitry. The conductive paths include first conductive interconnects within the first gaps and second conductive interconnects within the second gaps. The first and second conductive interconnects are laterally offset relative to one another.

公开(公告)号：US20240258167A1

公开(公告)日：2024-08-01

申请号：US18634809

申请日：2024-04-12

Applicant: Micron Technology, Inc.

Inventor： Trupti D. Gawai ,  David S. Pratt ,  Ahmed M. Elsied ,  David A. Kewley ,  Dale W. Collins ,  Raju Ahmed ,  Chelsea M. Jordan ,  Radhakrishna Kotti

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/528

CPC classification number: H01L21/76883 ,  H01L21/76816 ,  H01L23/5226 ,  H01L23/5283

Abstract: Methods of manufacturing semiconductor devices, and associated systems and devices, are disclosed herein. In some embodiments, a method of manufacturing a semiconductor device includes forming an opening in an electrically insulative material at least partially over a first electrically conductive feature and a second electrically conductive feature. The method can further include forming a ring of electrically conductive material around a sidewall of the insulative material defining the opening, wherein the ring of electrically conductive material includes (a) a first via portion over the first electrically conductive feature, (b) a second via portion over the second electrically conductive feature, and (c) connecting portions extending between the first and second via portions. Finally, the method can include removing the connecting portions of the ring of electrically conductive material to electrically isolate the first via portion from the second via portion.

公开(公告)号：US11515204B2

公开(公告)日：2022-11-29

申请号：US17136287

申请日：2020-12-29

Applicant: Micron Technology, Inc.

Inventor： Trupti D. Gawai ,  David S. Pratt ,  Ahmed M. Elsied ,  David A. Kewley ,  Dale W. Collins ,  Raju Ahmed ,  Chelsea M. Jordan ,  Radhakrishna Kotti

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/528

Abstract: Methods of manufacturing semiconductor devices, and associated systems and devices, are disclosed herein. In some embodiments, a method of manufacturing a semiconductor device includes forming an opening in an electrically insulative material at least partially over a first electrically conductive feature and a second electrically conductive feature. The method can further include forming a ring of electrically conductive material around a sidewall of the insulative material defining the opening, wherein the ring of electrically conductive material includes (a) a first via portion over the first electrically conductive feature, (b) a second via portion over the second electrically conductive feature, and (c) connecting portions extending between the first and second via portions. Finally, the method can include removing the connecting portions of the ring of electrically conductive material to electrically isolate the first via portion from the second via portion.

公开(公告)号：US20220208606A1

公开(公告)日：2022-06-30

申请号：US17136287

申请日：2020-12-29

Applicant: Micron Technology, Inc.

Inventor： Trupti D. Gawai ,  David S. Pratt ,  Ahmed M. Elsied ,  David A. Kewley ,  Dale W. Collins ,  Raju Ahmed ,  Chelsea M. Jordan ,  Radhakrishna Kotti

IPC: H01L21/768 ,  H01L23/528 ,  H01L23/522

Abstract: Methods of manufacturing semiconductor devices, and associated systems and devices, are disclosed herein. In some embodiments, a method of manufacturing a semiconductor device includes forming an opening in an electrically insulative material at least partially over a first electrically conductive feature and a second electrically conductive feature. The method can further include forming a ring of electrically conductive material around a sidewall of the insulative material defining the opening, wherein the ring of electrically conductive material includes (a) a first via portion over the first electrically conductive feature, (b) a second via portion over the second electrically conductive feature, and (c) connecting portions extending between the first and second via portions. Finally, the method can include removing the connecting portions of the ring of electrically conductive material to electrically isolate the first via portion from the second via portion.

公开(公告)号：US11978527B2

公开(公告)日：2024-05-07

申请号：US17693119

申请日：2022-03-11

Applicant: Micron Technology, Inc.

Inventor： Raju Ahmed ,  David A. Kewley ,  Dave Pratt ,  Yung-Ta Sung ,  Frank Speetjens ,  Gurpreet Lugani

IPC: H01L23/532 ,  G11C5/06

CPC classification number: G11C5/06 ,  H01L23/53257 ,  H01L23/5329

Abstract: Some embodiments include an integrated assembly having an interconnect over a first conductive structure and coupled with the first conductive structure. The interconnect includes a conductive core. The conductive core has a slender upper region and a wide lower region. The upper region joins to the lower region at a step. A liner laterally surrounds the lower region of the conductive core. The liner has an upper surface which is substantially coplanar with the step. An insulative collar is over and directly against both an upper surface of the step and the upper surface of the liner. The insulative collar laterally surrounds and directly contacts the slender upper region. A second conductive structure is over and directly against a region of the insulative collar, and is over and directly against an upper surface of the slender upper region. Some embodiments include methods of forming integrated assemblies.

公开(公告)号：US11545391B2

公开(公告)日：2023-01-03

申请号：US16787321

申请日：2020-02-11

Applicant: Micron Technology, Inc.

Inventor： Raju Ahmed ,  Frank Speetjens ,  Darin S. Miller ,  Siva Naga Sandeep Chalamalasetty ,  Dave Pratt ,  Yi Hu ,  Yung-Ta Sung ,  Aaron K. Belsher ,  Allen R. Gibson

IPC: H01L21/768 ,  H01L23/522

Abstract: Some embodiments include a method of forming an integrated assembly. An arrangement is formed to include a conductive pillar extending through an insulative mass. An upper surface of the conductive pillar is recessed to form a cavity. An insulative collar is formed within the cavity to line an outer lateral periphery of the cavity. A recessed surface of the conductive pillar is exposed at a bottom of the lined cavity. A conductive expanse is formed over the insulative mass. A portion of the conductive expanse extends into the cavity and is configured as an interconnect. The conductive expanse is patterned into multiple conductive structures. One of the conductive structures includes the interconnect.

公开(公告)号：US11328749B2

公开(公告)日：2022-05-10

申请号：US16718454

申请日：2019-12-18

Applicant: Micron Technology, inc.

Inventor： Raju Ahmed ,  David A. Kewley ,  Dave Pratt ,  Yung-Ta Sung ,  Frank Speetjens ,  Gurpreet Lugani

IPC: H01L23/532 ,  G11C5/06

Abstract: Some embodiments include an integrated assembly having an interconnect over a first conductive structure and coupled with the first conductive structure. The interconnect includes a conductive core. The conductive core has a slender upper region and a wide lower region. The upper region joins to the lower region at a step. A liner laterally surrounds the lower region of the conductive core. The liner has an upper surface which is substantially coplanar with the step. An insulative collar is over and directly against both an upper surface of the step and the upper surface of the liner. The insulative collar laterally surrounds and directly contacts the slender upper region. A second conductive structure is over and directly against a region of the insulative collar, and is over and directly against an upper surface of the slender upper region. Some embodiments include methods of forming integrated assemblies.

公开(公告)号：US20240282702A1

公开(公告)日：2024-08-22

申请号：US18652079

申请日：2024-05-01

Applicant: Micron Technology, Inc.

Inventor： Raju Ahmed ,  Radhakrishna Kotti ,  David A. Kewley ,  Dave Pratt

IPC: H01L23/528 ,  H01L23/522 ,  H10B61/00 ,  H10B63/00

CPC classification number: H01L23/528 ,  H01L23/5226 ,  H10B61/00 ,  H10B63/84

Abstract: Some embodiments include an integrated assembly having a base which includes first circuitry. Memory decks are over the base. Each of the memory decks has a sense/access line coupled with the first circuitry. The memory decks and base are vertically spaced from one another by gaps. The gaps alternate in a vertical direction between first gaps and second gaps. Overlapping conductive paths extend from the sense/access lines to the first circuitry. The conductive paths include first conductive interconnects within the first gaps and second conductive interconnects within the second gaps. The first and second conductive interconnects are laterally offset relative to one another.

公开(公告)号：US11990370B2

公开(公告)日：2024-05-21

申请号：US18048633

申请日：2022-10-21

Applicant: Micron Technology, Inc.

Inventor： Trupti D. Gawai ,  David S. Pratt ,  Ahmed M. Elsied ,  David A. Kewley ,  Dale W. Collins ,  Raju Ahmed ,  Chelsea M. Jordan ,  Radhakrishna Kotti

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/528

CPC classification number: H01L21/76883 ,  H01L21/76816 ,  H01L23/5226 ,  H01L23/5283

Abstract: Methods of manufacturing semiconductor devices, and associated systems and devices, are disclosed herein. In some embodiments, a method of manufacturing a semiconductor device includes forming an opening in an electrically insulative material at least partially over a first electrically conductive feature and a second electrically conductive feature. The method can further include forming a ring of electrically conductive material around a sidewall of the insulative material defining the opening, wherein the ring of electrically conductive material includes (a) a first via portion over the first electrically conductive feature, (b) a second via portion over the second electrically conductive feature, and (c) connecting portions extending between the first and second via portions. Finally, the method can include removing the connecting portions of the ring of electrically conductive material to electrically isolate the first via portion from the second via portion.